Modular Focal Plane Array Scalability via Stacked Dice
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Solution Overview
Problem
Conventional focal plane arrays (FPAs) face manufacturability challenges when increasing size to accommodate a larger field of view, as die yield decreases with larger die sizes, making it difficult to scale FPAs effectively.
Innovation Solution
A modular, scalable FPA design using arrays of integrated circuit dice, where each die includes pixel array circuitry and corresponding signal processing circuitry, allowing for stacking and interconnection to maintain desired pixel pitch across the enlarged array, utilizing techniques like Direct Bond Interconnect and bump bonding for efficient integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the die size is increased to accommodate a larger pixel array for expanded field of view, then the field of view and imaging area are improved, but the manufacturability and die yield deteriorate
Solution Approach 1:
The pixel array is divided into multiple smaller die, each containing a portion of the total pixels. These individual die are then assembled into a mosaic configuration to form the complete large-format pixel array. This segmentation allows each die to be manufactured with high yield while collectively achieving the desired large imaging area.
Solution Approach 2:
The patent transitions from a single-plane pixel array to a three-dimensional stacked architecture where multiple die are arranged in layers and interconnected via through-silicon vias (TSVs). This vertical stacking enables the system to achieve large effective pixel array area without requiring proportionally large individual die, thereby maintaining manufacturability.
2Area of stationary object
If the die size is increased to accommodate a larger pixel array, then the field of view is improved, but the signal processing capability becomes insufficient
Solution Approach 1:
Signal processing circuitry is distributed across multiple die rather than concentrated on a single large die. Each die contains its own signal processing units that handle data from local pixels, reducing the complexity burden on any single component while collectively providing comprehensive processing capability for the entire large-format array.
Solution Approach 2:
The patent implements a hierarchical processing architecture where signal processing occurs at multiple levels: individual pixels on each die, then intermediate processing within each die, and finally aggregate processing across the stacked die. This nested structure allows complex processing to be broken down into manageable stages distributed throughout the three-dimensional array.
Data Source
AI summary
A modular, scalable focal plane array is provided as an array of integrated circuit dice, wherein each die includes a given amount of modular pixel array circuitry. The array of dice effectively multiplies the amount of modular pixel array circuitry to produce a larger pixel array without increasing die size. Desired pixel pitch across the enlarged pixel array is preserved by forming die stacks with each pixel array circuitry die stacked on a separate die that contains the corresponding signal processing circuitry. Techniques for die stack interconnections and die stack placement are implemented to ensure that the desired pixel pitch is preserved across the enlarged pixel array.