Modular Fuses and Inductors for CMP Uniformity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in achieving uniformity during chemical mechanical planarization (CMP) processes due to CMP-induced topography, particularly 'dishing' effects, which can lead to short circuits and inefficiencies in metal removal from recessed areas, and the need for dummy structures that consume valuable space on integrated circuits.
Innovation Solution
The development of modular microelectronic circuit elements, including resistors, capacitors, and inductors, which can be designed in various geometries and configurations using a low-temperature copper patterning process and damascene fabrication, serving both as functional components and improving CMP uniformity, replacing the need for conventional dummy structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMP process is used to planarize wafer surface, then surface uniformity is improved, but dishing occurs causing non-uniformity in large metal fields
Solution Approach 1:
The patent segments large metal fields into smaller discrete metal features by introducing dummy metal structures. These dummy features break up the continuous large metal areas into smaller segments that are more uniformly removed during CMP, preventing dishing while maintaining overall surface planarity.
Solution Approach 2:
The patent applies local quality by placing dummy metal features specifically in large metal field areas where dishing occurs, rather than uniformly across the entire wafer. This targeted approach addresses the local CMP uniformity problem in specific regions without affecting other areas.
2Manufacturing precision
If dummy metal features are added to improve CMP uniformity, then CMP performance is improved, but valuable chip area is consumed
Solution Approach 1:
The patent makes the dummy metal features multi-functional by designing them to serve dual purposes: (1) improving CMP uniformity by breaking up large metal fields, and (2) providing additional functional metal interconnect structures that can be used for actual circuit routing. This eliminates the need for separate dummy structures and functional structures, as the same structures fulfill both roles.
3Adaptability or versatility
If fuses and antifuses are used to alter circuit connections, then circuit reconfigurability is improved, but additional circuit elements are required
Solution Approach 1:
The patent merges the functionality of fuses/antifuses with the existing dummy metal interconnect structures. Instead of adding separate fuse elements alongside the interconnect network, the fuse functionality is integrated directly into the metal interconnect layers themselves, allowing circuit reconfiguration without additional discrete fuse components.
Data Source
AI summary
Nanoscale efuses, antifuses, and planar coil inductors are disclosed. A copper damascene process can be used to make all of these circuit elements. A low-temperature copper etch process can be used to make the efuses and efuse-like inductors. The circuit elements can be designed and constructed in a modular fashion by linking a matrix of metal columns in different configurations and sizes. The number of metal columns, or the size of a dielectric mesh included in the circuit element, determines its electrical characteristics. Alternatively, the efuses and inductors can be formed from interstitial metal that is either deposited into a matrix of dielectric columns, or left behind after etching columnar openings in a block of metal. Arrays of metal columns also serve a second function as features that can improve polish uniformity in place of conventional dummy structures. Use of such modular arrays provides flexibility to integrated circuit designers.