Modular PLD Page Memory Architecture with Universal Bus Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional programmable logic device (PLD) architectures face challenges in modularity, scalability, and re-usability due to complex interconnections and the need for frequent modifications of building blocks, which complicates development and increases costs and schedules.
Innovation Solution
A scalable and modular bus controller-based PLD page memory architecture with a universal bus interface allows for data exchange between PLD modules and a bus controller, enabling flexible configuration, plug-and-play re-use, and dynamic module control through a sequence engine that processes instructions per clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional PLD architectures use complex interconnections and frequent modifications of building blocks, then functionality can be achieved, but modularity and scalability deteriorate
Solution Approach 1:
The PLD architecture is segmented into modular functional blocks that can be independently configured and connected through a standardized bus interface. Each functional block operates as an independent module that can be selectively activated, eliminating the need for complex point-to-point interconnections and enabling easy reconfiguration for different applications.
Solution Approach 2:
A universal bus interface is implemented that allows different functional blocks to communicate through a common standardized protocol. This universal interface enables the same bus controller to work with various PLD modules, providing multi-functionality and eliminating the need for application-specific interconnection designs.
2Adaptability or versatility
If conventional PLD architectures require frequent modifications of building blocks, then application-specific functionality can be achieved, but development costs and schedules worsen
Solution Approach 1:
The architecture provides preliminary configuration capabilities where the bus controller and functional blocks are pre-designed with standardized interfaces. This allows applications to be configured by selecting and connecting pre-built modules rather than modifying building blocks, significantly reducing development costs and time while maintaining application-specific functionality.
3Adaptability or versatility
If conventional PLD architectures lack scalability, then initial design can be simplified, but ability to support multiple applications deteriorates
Solution Approach 1:
The architecture introduces a hierarchical dimension with a bus controller layer managing multiple functional block layers. This dimensional organization allows the system to scale from simple to complex applications by adding or removing functional blocks without increasing interconnection complexity, as all blocks communicate through the standardized bus interface.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A bus controller-based page memory programmable logic device (PLD) architecture (100) includes a plurality of PLD modules (102a-102n) and a bus controller (104) in signal communication with the plurality of PLD modules via a universal bus interface (106a, 106b). Each PLD module include a PLD memory unit (112) configured to store first data. The bus controller includes bus memory unit (122) configured to store second data and includes a bus controller engine (120) configured to sequentially execute a set of bus controller instructions. One or both of the first data and the second data is transferred between the bus controller and a target PLD module among the plurality of PLD modules in response to sequentially executing the set of bus controller instructions.