MOF-Filled PCB Resin for Low CTE and Signal Integrity
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Solution Overview
Problem
Existing printed circuit boards (PCBs) face challenges in matching the coefficient of thermal expansion (CTE) with package substrates, leading to increased stress and solder joint failures, while reducing CTE often results in higher dielectric constants, making them unsuitable for high-speed I/O applications.
Innovation Solution
Incorporating metal organic frameworks (MOFs) as fillers within the PCB resin to achieve a low CTE and maintain or reduce the dielectric constant, thereby matching the CTE of the package substrate without the need for additional non-critical-to-function pins or adhesives.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If low CTE materials are inserted into the PCB to reduce the CTE and match the package substrate, then the CTE mismatch is reduced, but the dielectric constant increases which negatively impacts signal integrity
Solution Approach 1:
The patent changes the physical and chemical parameters of the PCB material by incorporating MOF fillers with specific properties (low CTE and low dielectric constant). The MOF fillers have a dielectric constant of less than 3.0 and CTE of 0-10 ppm/°C, which when combined with the resin matrix, produce a composite material that simultaneously achieves low CTE (matching package substrate) and low dielectric constant (maintaining signal integrity for high-speed I/O).
Solution Approach 2:
The patent creates a composite PCB material by combining resin with MOF (metal organic framework) fillers. This composite structure allows the PCB to inherit the low dielectric constant property from the MOF fillers while also achieving low CTE, thereby simultaneously satisfying both the CTE matching requirement and the signal integrity requirement for high-speed applications.
2Reliability
If the number of nCTF pins is increased to deal with CTE mismatch stress, then solder joint failure is reduced, but the area of the interconnect solution increases
Solution Approach 1:
The patent extracts the stress-mitigation function from the mechanical design (additional pins and adhesives) and transfers it to the material design. By incorporating MOF fillers into the PCB resin, the material itself provides CTE matching and stress reduction, eliminating the need for additional nCTF pins and adhesive applications, thereby reducing the interconnect area while maintaining solder joint reliability.
3Reliability
If adhesive is applied to high stress areas to mitigate CTE mismatch, then solder joint stress is reduced, but manufacturing cost and throughput are negatively impacted
Solution Approach 1:
The patent merges multiple functions into a single material component. The MOF-filled resin simultaneously provides: (1) CTE matching to reduce thermal stress, (2) low dielectric constant for signal integrity, and (3) structural integrity to replace adhesive applications. This consolidation eliminates separate adhesive application steps, reducing manufacturing complexity and improving throughput while maintaining stress resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of MOFs in PCBs reduces CTE to match the package substrate, lowers stress on interconnects, and maintains low dielectric constants, enabling compatibility with high-speed I/O applications while minimizing footprint and manufacturing costs.
Implementation Method 1
Metal organic frameworks (MOFs) filler for enabling low CTE and low dielectric constant PCB
Implementation Method 2
low dielectric constants
Data Source
AI summary
Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a printed circuit board (PCB), where the PCB comprises a glass weave, a resin, and metal organic frameworks (MOFs) disposed within the resin. In an embodiment, a package substrate is coupled to the PCB, and a die is coupled to the package substrate.