Molded Interconnect Memory Package with Through-Mold Via Routing
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Solution Overview
Problem
The challenge in electronic systems is to reduce the form factor and improve signal integrity by efficiently routing interconnections between integrated circuits, particularly in memory-down packaging approaches where signal routing lengths are long and lead to increased package form factor and signal integrity trade-offs.
Innovation Solution
The solution involves a memory-on-package (MOP) approach with through-mold vias (TMVs) and molded interconnects that allow for direct routing between memory dies and processor ICs, reducing the need for long signal paths through the motherboard and enabling a more compact form factor by stacking memory dies on a substrate with a mold layer and using smaller solder bumps for interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory dies are packaged using traditional motherboard routing, then signal routing is achieved, but signal routing length increases and package form factor increases
Solution Approach 1:
The patent implements through-mold vias (TMVs) that extend vertically through the mold compound layer, enabling signals to travel in the vertical dimension rather than horizontally across the motherboard. This dimensional transition significantly shortens signal routing length while maintaining signal integrity, directly resolving the contradiction between signal integrity and routing length.
Solution Approach 2:
The patent embeds conductive interconnect structures within the mold compound material itself, creating a nested configuration where interconnects are enclosed within the protective mold layer. This nesting approach allows signal routing to occur within the package structure rather than across the motherboard, reducing routing length while preserving signal quality.
2Ease of manufacture
If traditional packaging with long signal paths is used, then interconnection is achieved, but package form factor increases
Solution Approach 1:
By transitioning signal routing from horizontal motherboard paths to vertical through-mold via paths, the patent achieves interconnection within a compact three-dimensional space. This dimensional change enables the package to maintain full interconnection capability while dramatically reducing the horizontal footprint and overall form factor.
Solution Approach 2:
The patent combines multiple functions into the mold compound material, which simultaneously serves as structural encapsulation, electrical insulation, and signal transmission medium through embedded conductive interconnects. This merging eliminates the need for separate routing layers and reduces overall package area while maintaining interconnection capability.
3Ease of operation
If longer signal routing is used for memory interconnection, then connectivity is achieved, but signal integrity deteriorates
Solution Approach 1:
The vertical orientation of through-mold vias creates shorter, more direct signal paths compared to horizontal motherboard routing. This dimensional transition reduces signal path length and minimizes exposure to lossy board materials, thereby maintaining signal integrity while achieving full connectivity between memory dies and processor.
4Area of stationary object
If compact packaging is implemented, then form factor is reduced, but signal routing complexity increases
Solution Approach 1:
The patent simplifies signal routing complexity by nesting conductive interconnects within the mold compound during the molding process itself. This integrated approach eliminates the need for complex post-molding routing operations and reduces the number of separate manufacturing steps, thereby maintaining compact form factor while managing routing complexity.
Solution Approach 2:
The conductive interconnect structures are formed and positioned within the mold compound during the initial molding process, before final package assembly. This preliminary action simplifies subsequent assembly steps and reduces overall routing complexity, enabling compact packaging without proportionally increasing manufacturing complexity.
Data Source
AI summary
An electronic system includes a first substrate including first solder bumps on a bottom surface, the first solder bumps having a first solder bump surface opposite from the bottom surface; a processor integrated circuit (IC) die including at least one processor mounted on a top surface of the first substrate; and a companion component to the processor IC. The companion component includes a second substrate, second solder bumps, and third solder bumps. The second solder bumps include a second solder bump surface, and the third solder bumps include a third solder bump surface at a different height than the second solder bump surface. The second solder bump surface contacts the top surface of the first substrate and the third solder bump surface is at a same height as the first solder bump surface.