Barrier-Free Molybdenum MOL Interconnects for RC Delay Reduction
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Solution Overview
Problem
The challenge of increasing resistance-capacitance (RC) delay in integrated circuits (ICs) due to reduced interconnect dimensions necessitates improvements in interconnects and their fabrication methods to enhance signal routing efficiency and further scaling of ICs.
Innovation Solution
The implementation of barrier-free MOL interconnect structures using molybdenum and tungsten to reduce resistance in source/drain contacts and vias, which are fabricated through a bottom-up deposition process to ensure seamless and vertically profiled connections, thereby minimizing RC delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If interconnect dimensions are reduced to increase functional density, then the number of interconnected IC devices per chip area increases, but resistance-capacitance delay increases
Solution Approach 1:
The patent changes the material parameter from conventional copper to molybdenum-containing interconnects, which have lower resistivity and better scaling characteristics at reduced dimensions, thereby reducing RC delay while maintaining high functional density
Solution Approach 2:
The patent uses composite material structures including molybdenum-containing interconnects with barrier-free designs and integrated capacitor structures, combining multiple materials with complementary properties to simultaneously reduce resistance and capacitance
2Speed
If geometry size is reduced to achieve faster operating speeds, then signal travel distance decreases, but RC delay increases
Solution Approach 1:
The patent changes the electrical parameters of the interconnect material by using molybdenum-containing compositions with optimized resistivity and capacitance characteristics, ensuring that even at reduced geometry sizes, the RC delay remains minimized to maintain fast operating speeds
Solution Approach 2:
The patent employs barrier-free molybdenum-containing interconnect structures that replicate the beneficial electrical properties of ideal conductors at scaled dimensions, effectively copying the performance characteristics needed for fast operation without the RC delay penalties of conventional materials
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of molybdenum-containing interconnects reduces interconnect resistance, improving IC performance by minimizing RC delay and enhancing signal routing efficiency, thus supporting further scaling of ICs.
Implementation Method 1
The implementation of barrier-free MOL interconnect structures using molybdenum and tungsten to reduce resistance in source/drain contacts and vias
Implementation Method 2
fabricated through a bottom-up deposition process to ensure seamless and vertically profiled connections
Data Source
AI summary
Middle-of-line (MOL) interconnects and techniques for forming the MOL interconnects are disclosed. An exemplary MOL interconnect structure includes a barrier-free source/drain contact, a barrier-free source/drain via, and a barrier-free gate via disposed in an insulator layer. The barrier-free source/drain contact is disposed on an epitaxial source/drain, and the barrier-free source/drain contact includes tungsten, molybdenum, or a combination thereof. The barrier-free source/drain via is disposed on the barrier-free source/drain contact and the barrier-free source/drain via includes molybdenum. The barrier-free gate via is disposed on a gate stack disposed adjacent to the epitaxial source/drain, and the barrier-free gate via includes tungsten, molybdenum, or a combination thereof. A width of the barrier-free source/drain via and/or the barrier-free gate via may be less than about 16 nm. The barrier-free source/drain via and/or the barrier-free gate via may be formed at the same time (e.g., by a same bottom-up deposition).