Monolithic 3D IC Interconnects with Variable Dimensions
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Solution Overview
Problem
As device sizes in monolithic integrated circuits (ICs) approach limits due to lateral scaling, achieving further transistor density becomes impractical, prompting the need for vertical scaling through three-dimensional integration to overcome capacitance and quantum variability challenges.
Innovation Solution
A monolithic three-dimensional IC structure is developed with a plurality of first and second interconnects on opposite sides of a device layer, where the dimensions of the second interconnects vary to accommodate specific functions, such as power distribution and global clock distribution, enabling efficient access and operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If lateral scaling of IC dimensions is continued, then transistor density increases, but capacitance and quantum variability become prohibitively high
Solution Approach 1:
The patent transitions from two-dimensional planar scaling to three-dimensional vertical stacking by placing device layers above and below the substrate. This dimensional change allows continued transistor density improvement without further lateral scaling, thereby avoiding the capacitance and quantum variability issues that plague sub-20nm planar devices.
2Quantity of substance
If vertical scaling through three-dimensional integration is implemented, then transistor density increases beyond planar limits, but interconnect complexity and manufacturing difficulty increase
Solution Approach 1:
The interconnect system is segmented into multiple independent layers: first interconnects on the substrate, second interconnects in the interconnect region, and third interconnects on the opposite side. This segmentation allows each layer to be optimized for specific functions (power, ground, signals) and simplifies manufacturing by enabling separate formation processes for each interconnect layer.
Solution Approach 2:
The patent utilizes the vertical dimension to stack interconnect layers at different heights above and below the device layer. This three-dimensional interconnect architecture reduces routing complexity by providing additional vertical pathways for signal and power distribution, eliminating the need for excessively complex planar routing.
3Ease of manufacture
If uniform interconnect dimensions are used throughout the structure, then manufacturing is simplified, but optimized power distribution and signal routing become difficult
Solution Approach 1:
The patent implements local quality by varying interconnect dimensions according to functional requirements. Power interconnects are made thicker to handle high current, while signal interconnects use optimized thickness for impedance control. Each interconnect layer can have different material compositions and geometries tailored to its specific electrical function, achieving both manufacturing feasibility and functional optimization.
Data Source
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AI summary
A method including forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and forming contact points to the second plurality of interconnects, the contact points operable for connection to an external source. An apparatus including a substrate including a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and contact points coupled to the second plurality of interconnects, the contact points operable for connection to an external source.