Monolithic BAW Resonator Integration to Reduce Parasitic Effects
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Solution Overview
Problem
Existing semiconductor structures face challenges with parasitic effects and increased manufacturing costs due to separate fabrication of resonators and IC chips, leading to degraded Q factor performance and larger package sizes.
Innovation Solution
A monolithic-integrated bulk acoustic wave (BAW) resonator is integrated into the IC chip using a modified metal-insulator-metal (MIM) capacitor manufacturing flow within the CMOS process, reducing parasitic effects and simplifying packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If resonators are fabricated separately from IC chips, then manufacturing flexibility is maintained, but parasitic effects increase and Q factor degrades
Solution Approach 1:
The patent merges the resonator fabrication process with the IC chip manufacturing process by integrating the resonator structure into the CMOS fabrication flow. The resonator is formed within the same semiconductor substrate using the same processing steps, eliminating the need for separate resonator fabrication and bonding operations. This integration reduces parasitic effects at the interface between separate components and improves the Q factor by minimizing energy loss at connection points.
2Volume of stationary object
If resonators are integrated into IC chips, then package size is reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent applies universality by designing a manufacturing process that serves multiple functions: the same CMOS fabrication steps that create transistors and interconnections also create the resonator structure. The cavity, piezoelectric layers, and conductive structures are formed using standard semiconductor processing techniques already present in the fabrication line, making the process scalable and compatible with existing manufacturing infrastructure.
3Ease of manufacture
If separate fabrication processes are used for resonators and IC chips, then process optimization is easier, but manufacturing costs increase
Solution Approach 1:
The patent combines resonator and IC chip fabrication into a single integrated process flow, eliminating the need for separate manufacturing lines, multiple bonding steps, and additional assembly operations. This merger reduces manufacturing costs by utilizing existing CMOS fabrication capabilities and improves productivity by producing both components simultaneously in the same fabrication run.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved Q factor performance, reduced manufacturing costs, and a smaller package size by integrating the resonator directly into the IC chip, minimizing parasitic effects and leveraging standard CMOS packaging processes.
Implementation Method 1
a piezoelectric layer over the cavity structure
Data Source
AI summary
Disclosed are techniques for an integrated circuit (IC) that includes one or more transistors on a substrate and an interconnection structure on the one or more transistors. The interconnection structure includes a semiconductor structure embedded in the interconnection structure. In an aspect, the semiconductor structure includes a cavity structure, a piezoelectric layer over the cavity structure, an upper conductive structure on the piezoelectric layer, and a first contact structure on the upper conductive structure. In an aspect, the cavity structure includes a bottom that is a part of a first etch stop layer over a substrate, a top that is a part of a second etch stop layer over the first etch stop layer, one or more sidewalls connecting the bottom and the top of the cavity structure, and a cavity between the top and the bottom of the cavity structure and surrounded by the one or more sidewalls.