Monolithic Serial NOR Flash Wide IO Bus Bandwidth
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Solution Overview
Problem
Conventional serial NOR flash memory devices face limitations in increasing data bandwidth without increasing power consumption and controller complexity, particularly in multi-die configurations which require separate controllers for each die and result in higher assembly and operational costs.
Innovation Solution
A monolithic serial NOR flash memory device with a wide input-output bus, utilizing a single semiconductor die and transferring commands through a subset of IO pins while data is transmitted over a larger number of pins, doubling the data bandwidth without increasing power consumption or controller complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple NOR flash memory dies are packaged together to increase data bandwidth, then data bandwidth is improved, but power consumption increases
Solution Approach 1:
The patent merges multiple memory dies into a single monolithic chip structure, combining the functionality of multiple independent dies into one integrated unit. This allows the system to achieve high data bandwidth through a wide input-output bus (16 or more pins) while consuming power similar to a single die, thus resolving the contradiction between bandwidth and power consumption.
2Productivity
If multiple NOR flash memory dies are packaged together to increase data bandwidth, then data bandwidth is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple memory dies into a single monolithic chip, which simplifies the overall system architecture. Instead of requiring separate controllers for each die, the single chip integrates all memory functions, reducing controller complexity while maintaining high data bandwidth through the wide input-output bus interface.
3Productivity
If multiple NOR flash memory dies are packaged together to increase data bandwidth, then data bandwidth is improved, but manufacturing cost increases
Solution Approach 1:
The patent merges multiple memory dies into a single monolithic chip structure, eliminating the need for complex multi-chip packaging and assembly processes. This single-chip approach reduces assembly costs, simplifies manufacturing, while still achieving high data bandwidth through the wide input-output bus interface.
4Productivity
If operating frequency is increased to increase data output bandwidth, then data bandwidth is improved, but technology limitations are encountered
Solution Approach 1:
Instead of increasing data bandwidth by raising operating frequency (temporal dimension), the patent expands the bandwidth by increasing the number of parallel input-output pins (spatial dimension). This dimensional shift allows high bandwidth achievement without being constrained by frequency-related technology limitations such as signal integrity and power consumption at high frequencies.
Data Source
AI summary
A monolithic serial NOR Flash memory device includes a single semiconductor memory die with a wide input-output (IO) bus. More specifically, the monolithic serial NOR Flash memory device is configured with an input-output (IO) bus including N number of IO terminals, also referred herein as IO pins. The memory device of the present disclosure transfers commands through a subset of the N IO terminals while transferring data through all of the N IO terminals. In one example, the subset of IO terminals is N/2 IO terminals. In one example, the serial NOR Flash memory device is implemented as a serial octal (base 8) NOR flash memory device. As thus configured, the serial octal NOR flash memory device of the present disclosure transfers command though 8 IO pins, transfers address through 8 IO pins or 16 IO pins, and transfers data though 16 IO pins.