Monolithic PMUT CMOS Integration via Coplanar Passivation
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Solution Overview
Problem
Current semiconductor fabrication techniques for high-frequency piezoelectric micromachined ultrasonic transducers (PMUTs) are costly and complex due to wafer bonding and require intricate process flows for forming elastic, sealing, and passivation layers, leading to issues like phase signal loss and bonding yield factors.
Innovation Solution
A method for forming a monolithic integrated PMUT and CMOS with a coplanar elastic and passivation layer in a single step without wafer bonding, involving a CMOS wafer with a metal layer, dielectric, sacrificial, and piezoelectric layers, where vias are formed to create an open cavity sealed by a dielectric layer, forming an elastic and passivation layer simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wafer bonding is used to integrate PMUT and CMOS, then device integration is achieved, but fabrication cost increases and process complexity increases
Solution Approach 1:
The patent merges the elastic layer, sealing layer, and passivation layer into a single coplanar structure formed in one fabrication step. This eliminates the need for separate wafer bonding processes and multiple sequential layer formations, directly reducing fabrication process complexity while maintaining device integration reliability
Solution Approach 2:
The coplanar layer structure serves multiple functions simultaneously: it provides elastic support, seals the cavity, and offers passivation protection. This multi-functionality eliminates the need for separate dedicated layers for each function, simplifying the overall fabrication process while achieving reliable integration
2Reliability
If wafer bonding is used to integrate PMUT and CMOS, then device integration is achieved, but fabrication cost increases
Solution Approach 1:
The patent combines multiple layer formation operations into a single coplanar structure fabrication step. This merging reduces the number of discrete manufacturing operations, material deposition steps, and process control requirements, directly lowering fabrication costs while maintaining integration reliability
Solution Approach 2:
The patent extracts and eliminates the wafer bonding step from the fabrication process. By removing this costly and complex intermediate process while maintaining integration through the coplanar structure, fabrication costs are reduced without compromising device reliability
3Reliability
If separate layers for elastic, sealing, and passivation are formed, then device functionality is achieved, but process flow complexity increases
Solution Approach 1:
The patent merges three separate functional layers (elastic, sealing, and passivation) into a single coplanar structure. This consolidation maintains all required device functionalities while reducing the process flow from multiple sequential layer depositions to a single integrated formation step, significantly simplifying the manufacturing process
4Strength
If wafer bonding is used for PMUT integration, then bonding strength is achieved, but phase signal loss occurs
Solution Approach 1:
The patent extracts and eliminates the wafer bonding process from the fabrication sequence. By removing the bonding interface that causes phase signal loss, the invention maintains structural integrity through the coplanar integrated structure without introducing the harmful phase shifts associated with bonded interfaces
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process, reduces costs, and minimizes phase signal loss by integrating PMUT and CMOS without wafer bonding, enabling more efficient and cost-effective high-frequency PMUT production with improved bonding yield.
Implementation Method 1
forming a piezoelectric layer over the CMOS wafer
Data Source
AI summary
A method of forming a monolithic integrated PMUT and CMOS with a coplanar elastic, sealing, and passivation layer in a single step without bonding and the resulting device are provided. Embodiments include providing a CMOS wafer with a metal layer; forming a dielectric over the CMOS; forming a sacrificial structure in a portion of the dielectric; forming a bottom electrode; forming a piezoelectric layer over the CMOS; forming a top electrode over portions of the bottom electrode and piezoelectric layer; forming a via through the top electrode down to the bottom electrode and a second via down to the metal layer through the top electrode; forming a second metal layer over and along sidewalls of the first and second via; removing the sacrificial structure, an open cavity formed; and forming a dielectric layer over a portion of the CMOS, the open cavity sealed and an elastic layer and passivation formed.