Decorative Surface Effects TRIZ Cases

Epitaxial antistiction bumps in MEMS buried cavities limit contact to small regions, preventing irreversible stiction without increasing membrane stiffness.

Segmented photolithography with stacked masks overcomes photoresist trapping in deep trenches, ensuring uniform coating for high aspect ratio structures.

Selective laser sintering creates precise patterns in protective layers, preventing underlying metallic surface damage and reducing production reject rates.

A dual organic polymer layer system forms precise patterns using a silicon-containing mask.

Lowering surface dopant levels prevents harmful reactions between titanium hard masks and fluorine, reducing bevel defects.

A MEMS sensor package uses a side wall port to admit fluid into the cavity without obstructing the opening with encapsulant.

Selective gas permeation allows precise pressure control in encapsulated devices without getter capacity limits.

Ultrasonic welding bonds fire-retardant paper and foam layers into an ultra-lightweight panel that meets aircraft heat release rate standards.

Closed curve conductive structures in the wire grid polarizing plate improve light efficiency by reflecting wasted polarized light back for reuse.

Segmented composite wafers prevent short circuits during anodic bonding, ensuring hermetic seals for MEMS devices.

Segmented embossing devices apply uniform lacquer layers to rounded corners without reducing cycle speed or increasing material waste.

A free floating rocker MEMS mirror uses adhesion to hold stable positions without mechanical springs.

Thermal printing generates micro-perforations in a bi-layer resist to enable permanent glass etching without liquid adhesive interference.

Partitioning thick deposited films into discrete patterned sections before thermal processing.

A coplanar elastic and passivation layer forms simultaneously with a piezoelectric micromachined ultrasonic transducer on a CMOS wafer.

Removing the substrate from traditional packaging structures reduces package thickness to the sensor level while maintaining electrical connections.

A polymer layer supports a chip with a switching structure penetrating the substrate, reducing production complexity and increasing durability.

Porous metal mesh caps block contaminants and shield MEMS sensors from EMI, maintaining acoustic access for reliable operation.

Sever encapsulated elevated conductors to create vertical interconnects, eliminating through-silicon vias and reducing manufacturing costs.

Selective CO to CO2 flow ratios in plasma ashing reduce sidewall damage and pitting, improving critical dimension uniformity during mask removal.

Porous low-k dielectric cavity walls provide continuous gas supply to resolve insufficiency in sealed MEMS device environments.

Separate ink-jet printing of UV resin and metallic powder avoids nozzle clogging while achieving a deep three-dimensional metallic appearance.

A wafer level packaging method uses polysilicon electrodes to bond a MEMS resonator element between wafers.

Low-temperature metal deposition prevents outgassing and leak paths, allowing the MEMS device to maintain consistent internal pressure.

Multi-level tapered write poles increase magnetic field strength by 4% and reduce cross-track flux, enabling higher recording area densities.

A MEMS pressure sensor uses stacked buried cavities to create distinct sensitive regions for piezoresistive detection.

Bulk etching creates large-diameter channels that reduce pressure drop while maintaining low device volume.

Flip-chip bumps and through-mold vias replace fragile wire bonds, reducing package volume while maintaining electrical reliability.

Nano interstices embedded in channel walls enhance surface wettability and capillary action, eliminating the need for plasma or chemical surface treatments.

Vapor-phase deposition forms uniform self-assembled monolayers on microarray substrates, resolving concentration variations inherent in liquid dipping methods.

Wafer level packaging reduces manufacturing costs and improves CMOS compatibility by segmenting the process into distinct stages for via formation and bonding.

Deposition forms electrodes over a BEOL stack, avoiding etch errors and out-gassing that degrade pressure accuracy.

A MEMS capacitive pressure sensor uses a 3D electrode structure with conductive sidewalls to increase capacitance.

Anode bonding joins a structure reinforcing layer to a MEMS wafer, preventing edge collapsing during cutting and boosting yield rates.

Two-stage thermal annealing grafts polymer brushes into trenches to create chemical contrast, enabling nanoscale pattern dimensions below ten nanometers.

Chemical etching trims upper wafers via a sacrificial pedestal, eliminating mechanical damage and particle contamination on the lower wafer.

Carrier layer topography counteracts capillary forces during drying, ensuring homogeneous particle distribution and consistent measuring signals.