Wafer Level Packaging with Through Silicon Vias
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Solution Overview
Problem
Existing wafer level packaging techniques are expensive and not fully compatible with current CMOS fabrication processes, limiting their effectiveness in accommodating small semiconductor device sizes and increasing complexity in processing and manufacturing.
Innovation Solution
A method of wafer level packaging that involves bonding two semiconductor wafers with different materials using bonding pads, forming through silicon vias for electrical connections, and using copper plating to reduce manufacturing costs and increase interconnect design flexibility, while hermetically sealing MEMS devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing wafer level packaging techniques are used, then packaging can be performed at wafer level, but manufacturing cost increases and compatibility with CMOS fabrication processes decreases
Solution Approach 1:
The packaging process is segmented into distinct stages: forming through-silicon vias in the first substrate, bonding the first substrate to the second substrate, and then completing interconnect formation after bonding. This segmentation allows each stage to be optimized independently and performed using standard CMOS-compatible processes, reducing overall manufacturing cost while maintaining wafer-level packaging efficiency.
Solution Approach 2:
Through-silicon vias are formed in the first substrate before bonding to the second substrate. This preliminary action enables subsequent interconnect formation to proceed more efficiently and with lower cost, as the complex via formation is completed when the substrate is still accessible and can be processed using standard CMOS techniques rather than requiring post-bonding complex processing.
2Productivity
If existing wafer level packaging techniques are used, then packaging can be performed at wafer level, but compatibility with CMOS fabrication processes decreases
Solution Approach 1:
The process is divided into CMOS-compatible stages: through-silicon via formation using standard etching and filling processes, wafer bonding using established bonding techniques, and post-bonding interconnect completion. Each stage uses processes that are compatible with existing CMOS fabrication capabilities, enabling seamless integration into standard manufacturing flows.
Solution Approach 2:
The first substrate acts as an intermediary that receives through-silicon via formation processing before bonding to the second substrate. This intermediary approach allows complex via formation to be performed using CMOS-compatible processes on the first substrate, which then serves as a pre-prepared platform for bonding and final interconnect formation, bridging the gap between via formation requirements and bonding requirements.
3Reliability
If traditional packaging methods are used, then electrical connections can be established, but real-estate requirements increase
Solution Approach 1:
The through-silicon vias are formed to extend through the first substrate and make contact with metal structures on the second substrate, creating a nested arrangement where interconnect elements are integrated within the substrate thickness rather than requiring additional lateral space. This nesting approach establishes reliable electrical connections while minimizing the overall packaging footprint.
Solution Approach 2:
The solution transitions from planar interconnect routing to three-dimensional vertical routing through the substrate. Through-silicon vias provide vertical electrical pathways that penetrate the substrate thickness, enabling connections to be made in the vertical dimension rather than requiring extensive lateral routing, thereby reducing the real-estate requirements on the wafer surface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs, increases packaging efficiency, and provides reliable electrical connections with reduced real-estate requirements, making it more compatible with advanced CMOS and MEMS integration.
Implementation Method 1
bonding a front surface of a first substrate to a second substrate
Implementation Method 2
copper plating to reduce manufacturing costs and increase interconnect design flexibility
Data Source
AI summary
A method of forming a semiconductor device package includes bonding a front surface of a first substrate to a second substrate, and thinning a back surface of the first substrate. The method includes depositing and patterning a dielectric layer on the thinned back surface of the first substrate, and etching the first substrate after the depositing and the patterning of the dielectric layer are performed to form a through silicon via to enable electrical connection with a first level metal of the first substrate. The method includes depositing an isolation layer to line the through silicon via is formed, and etching the isolation layer at the bottom of the through silicon via. The method includes depositing a conductive layer to line the through silicon via after the isolation layer at the bottom of the through silicon via is etched, and deposited a copper film over the conductive layer.