Wafer Level Packaging MEMS Resonator Hermetic Seal
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Solution Overview
Problem
Current wafer level packaging technologies face challenges in integrating fabrication and packaging processes, often requiring complex schemes that result in area penalties and compatibility issues with device formation methods.
Innovation Solution
A method for wafer level packaging that involves providing a substrate with a buried oxide layer and top oxide layer, etching to form openings and a MEMS resonator element, filling with polysilicon to create electrodes, bonding these electrodes to a CMOS or carrier wafer, and sealing the MEMS device between a capping wafer and the semiconductor device, allowing for a robust and hermetic seal without additional area loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If current wafer level packaging methods are used, then device packaging is achieved, but area penalties occur and device sizes increase
Solution Approach 1:
The patent merges the fabrication and packaging processes into a unified wafer-level operation. Multiple devices are packaged simultaneously at the wafer level rather than individually, eliminating area penalties and reducing overall device size while maintaining packaging efficiency
Solution Approach 2:
The patent transitions from traditional two-dimensional packaging to three-dimensional wafer-level packaging. By utilizing the vertical dimension and stacking multiple layers, the patent achieves higher density without increasing the footprint area, thereby resolving the area penalty issue
2Reliability
If complicated packaging schemes are implemented, then device protection is achieved, but process compatibility issues arise with fabrication methods
Solution Approach 1:
The patent develops a universal packaging scheme that is compatible with multiple fabrication processes including CMOS, bipolar, and MEMS. The same packaging methodology can be applied across different device types and fabrication techniques, achieving device protection without compromising ease of manufacture
Solution Approach 2:
The patent modifies packaging parameters and process conditions to achieve compatibility with various fabrication methods. By adjusting temperature, pressure, and material selection parameters, the packaging process can be adapted to work with different fabrication techniques while maintaining reliable device protection
3Reliability
If additional testing at wafer level is performed, then electrical properties are enhanced, but device complexity increases
Solution Approach 1:
The patent performs electrical testing and characterization at the wafer level before final packaging. This preliminary action allows for early detection and correction of electrical property issues, enhancing reliability while avoiding the need for complex post-packaging testing and remediation procedures
Data Source
AI summary
A method of wafer level packaging includes providing a substrate including a buried oxide layer and a top oxide layer, and etching the substrate to form openings above the buried oxide layer and a micro-electro-mechanical systems (MEMS) resonator element between the openings, the MEMS resonator element enclosed within the buried oxide layer, the top oxide layer, and sidewall oxide layers. The method further includes filling the openings with polysilicon to form polysilicon electrodes adjacent the MEMS resonator element, removing the top oxide layer and the sidewall oxide layers adjacent the MEMS resonator element, bonding the polysilicon electrodes to one of a complementary metal-oxide semiconductor (CMOS) wafer or a carrier wafer, removing the buried oxide layer adjacent the MEMS resonator element, and bonding the substrate to a capping wafer to seal the MEMS resonator element between the capping wafer and one of the CMOS wafer or the carrier wafer.