Monolithic Semiconductor Chip Array with Rear-Side Contacts
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Solution Overview
Problem
Existing semiconductor chip production methods for optoelectronic applications, such as LEDs, require multiple individual chips to be positioned and mounted separately on a carrier, which is inefficient and labor-intensive.
Innovation Solution
A semiconductor chip with multiple individually drivable functional regions, each with p-contacts and n-contacts on the rear side, allowing for simultaneous mounting and electrical connection to a carrier, eliminating the need for separate positioning of individual chips, and enabling series or parallel connections of regions for enhanced functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If multiple individual semiconductor chips are positioned and mounted separately on a carrier, then each chip can be individually contacted and connected, but the production process becomes complex and labor-intensive
Solution Approach 1:
The patent merges multiple individual semiconductor chips into a single integrated chip structure containing multiple functional regions. Each functional region corresponds to one chip but all regions are fabricated and mounted as one unit, eliminating the need for separate positioning and mounting operations while maintaining individual electrical contact capability through the conductive layer structure
Solution Approach 2:
The single semiconductor chip is segmented into multiple functional regions, each with its own contact structure. The conductive layer is also segmented into multiple regions that can be selectively connected to different functional regions, allowing individual control while simplifying mounting
2Productivity
If multiple individual semiconductor chips are positioned and mounted separately on a carrier, then each chip can be individually contacted, but the positioning and mounting time increases
Solution Approach 1:
Multiple functional regions are combined into a single chip that is mounted in one operation. The entire array of functional regions is positioned and mounted simultaneously as one unit, dramatically reducing the time required compared to sequential mounting of individual chips
3Adaptability or versatility
If multiple individual semiconductor chips are used, then high voltage or parallel connections can be achieved, but the arrangement and connection process becomes more complex
Solution Approach 1:
The conductive layer is designed with different connection configurations in different local regions. Some areas of the conductive layer are configured for series connections between functional regions, while other areas enable parallel connections, allowing both connection types to be achieved within a single simplified chip structure
Data Source
AI summary
A semiconductor chip (10) is provided which comprises:a semiconductor layer sequence (20) with a p-type semiconductor region (5) and an n-type semiconductor region (3),a plurality of p-contacts (11a, 11b), which are connected electrically conductively with the p-type semiconductor region (5), anda plurality of n-contacts (12a, 12b), which are connected electrically conductively with the n-type semiconductor region (3), wherein:the p-contacts (11a, 11b) and the n-contacts (12a, 12b) are arranged on a rear side of the semiconductor chip (10),the semiconductor chip (10) comprises a plurality of regions (21, 22) arranged adjacent one another, andthe regions (21, 22) each comprise one of the p-contacts (11a, 11b) and one of the n-contacts (12a, 12b).