Monolithic Silicon Bridge Stack for 3D Device Integration
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Solution Overview
Problem
The miniaturization of semiconductive devices poses challenges in assembly due to shrinking device and package sizes, requiring innovative solutions for efficient integration and communication between stacked dice without increasing footprint or contact lengths.
Innovation Solution
A monolithic silicon bridge stack is implemented, utilizing a baseband processor die as a substrate and hybrid silicon bridge, with through-silicon vias (TSVs) and redistribution layers (RDLs) to facilitate communication and power/ground contacts between stacked devices, reducing contact distances and eliminating the need for a dedicated memory controller hub.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If semiconductive devices are miniaturized to reduce package size, then device footprint is reduced, but assembly complexity and difficulty increase
Solution Approach 1:
The patent transitions from planar device arrangement to three-dimensional stacking configuration. Multiple semiconductive devices are arranged vertically in stacked layers rather than side-by-side in a single plane, enabling significant footprint reduction while maintaining assembly feasibility through standardized vertical interconnection processes
Solution Approach 2:
The patent implements a nested stacking architecture where smaller devices are positioned within the footprint boundary of larger devices in adjacent layers. This nested arrangement allows multiple devices to occupy overlapping horizontal spaces at different vertical levels, maximizing space utilization and reducing overall package footprint
2Area of stationary object
If devices are stacked closer together to reduce footprint, then package area is reduced, but contact lengths between devices increase
Solution Approach 1:
The patent introduces an intermediary substrate layer positioned between stacked devices to provide centralized interconnection points. This intermediary layer acts as a mediator that redistributes electrical contacts, allowing shorter individual contact lengths between adjacent devices while maintaining overall connectivity through the substrate's redistribution network
Solution Approach 2:
The patent segments the interconnection function into multiple stages: direct contacts from upper devices to the intermediary substrate, and separate contacts from lower devices to the same substrate. This segmentation breaks down long direct contact paths into shorter sequential segments, reducing overall contact length and associated resistance
3Quantity of substance
If multiple devices are integrated into a compact stack, then device density increases, but bandwidth and communication performance deteriorate
Solution Approach 1:
The patent implements local quality optimization by providing dedicated, short-contact interconnection paths for high-bandwidth communication between specific device pairs in the stack. Rather than using shared or long-distance connections, each critical communication path has its own optimized contact route through the intermediary substrate, maintaining high bandwidth despite increased device density
Data Source
AI summary
A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.