Monolithic Die Integration for SRAM Logic Density
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Solution Overview
Problem
The scaling of SRAM and logic circuits in AI chips is hindered by increased die size due to interconnection complexities and parasitic junctions, leading to inefficiencies and malfunctions, especially at technology nodes below 28nm, where miniaturization results in larger areas and power consumption issues, limiting the integration of high-performance computing and large storage volume on a single chip.
Innovation Solution
The integration system employs a monolithic die design with a processing unit and multiple SRAM arrays, allowing for direct connections between interconnection layers without intermediate layers, and utilizing localized isolations to reduce latch-up and enhance SRAM cell density, enabling more efficient and compact integration of logic and SRAM circuits within the same die area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If SRAM and logic circuits are scaled down to increase integration density, then device density improves, but parasitic junctions increase causing malfunctions and larger effective area
Solution Approach 1:
The patent divides the SRAM cell into segmented regions with localized isolations between them. This segmentation approach reduces the interaction between adjacent transistors, minimizing parasitic junction effects while maintaining high integration density. The isolations act as boundaries that prevent harmful electrical interactions between closely spaced circuit elements.
Solution Approach 2:
The patent introduces localized isolations at specific positions between adjacent transistors within the SRAM cell. Rather than uniformly increasing spacing throughout the entire cell, the isolation structures are strategically placed only where parasitic junctions form, providing targeted mitigation of harmful effects while preserving overall cell compactness.
2Reliability
If interconnection layers are increased to reduce parasitic effects, then reliability improves, but die area increases
Solution Approach 1:
The patent addresses interconnection challenges by transitioning from a planar two-dimensional layout to a three-dimensional structure with interconnection layers at different vertical levels. Through-silicon vias (TSVs) enable vertical interconnections between layers, allowing signals to traverse the die in the vertical dimension rather than requiring larger horizontal routing paths, thus maintaining compact die area while improving reliability.
Solution Approach 2:
The patent implements a nested interconnection architecture where multiple interconnection layers are stacked vertically, with each layer containing conductors that are embedded within or adjacent to other layers. This nested arrangement allows dense packing of interconnection pathways in the vertical dimension, providing multiple routing options without increasing the horizontal die footprint.
3Speed
If technology nodes are shrunk to increase computing performance, then processing speed improves, but manufacturing complexity and power consumption increase
Solution Approach 1:
The patent employs advanced parameter optimization in the SRAM cell design, including adjusted transistor width-to-length ratios, optimized well doping profiles, and tuned isolation structure dimensions. These parameter changes enable the cell to function reliably at scaled technology nodes by compensating for process variations and reduced voltage margins, thereby achieving high processing speed without proportionally increasing manufacturing complexity.
4Quantity of substance
If SRAM cell area is reduced to increase density, then storage density improves, but latch-up susceptibility increases
Solution Approach 1:
The patent introduces localized isolation structures as intermediary elements between adjacent n-type and p-type transistors in the SRAM cell. These isolations act as mediators that physically separate the transistor regions, blocking the formation of parasitic bipolar junction transistors that cause latch-up. The isolations enable dense transistor packing while maintaining latch-up immunity through this intermediate protective structure.
Data Source
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AI summary
An integration system includes a first monolithic die and a second monolithic die. The first monolithic die has a processing unit circuit formed therein and the second monolithic die has a plurality of SRAM arrays formed therein. The second monolithic die comprises at least 2G Bytes and the first monolithic die is electrically connected to the second monolithic die.