Split Gate MONOS Element Model with Variable Resistor Gap
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Solution Overview
Problem
The existing element models for split gate type MONOS non-volatile memory cells face accuracy issues in circuit simulation due to inaccuracies in representing cell current, temperature dependency, and differences in transistor characteristics between selection and memory gates, leading to difficulties in modeling and simulating the behavior of these memory elements effectively.
Innovation Solution
The introduction of a variable resistor model that simulates the parasitic resistance in the gap region between the selection and memory gates, which depends on both selection gate voltage and memory gate voltage, is used to enhance the accuracy of circuit simulation by accurately representing the parasitic resistance and its temperature dependence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a simple series coupling of two MOSFET models is used to represent split gate memory, then the device complexity is low, but the measurement precision of cell current simulation is insufficient
Solution Approach 1:
The element model is segmented into three distinct components: a first MOSFET model for the selection gate transistor, a second MOSFET model for the memory gate transistor, and a variable resistor model for the gap region parasitic resistance. This segmentation allows each component to be modeled independently with appropriate precision, improving overall simulation accuracy without requiring complete redesign of the entire model.
Solution Approach 2:
A variable resistor model is introduced as an intermediary element between the two MOSFET models to represent the parasitic resistance in the gap region. This intermediary component captures the electrical characteristics of the gap region that cannot be represented by standard MOSFET models alone, thereby improving measurement precision while maintaining clear model boundaries.
2Reliability
If existing MOSFET models are used without modification, then the ease of manufacture of the model is high, but the reliability of temperature dependency representation is poor
Solution Approach 1:
The variable resistor model incorporates temperature-dependent parameters that allow the parasitic resistance to vary with temperature according to the relationship Rgap(T) = Rgap(T0) × (1 + α(T - T0)). This parameter change approach enables accurate temperature dependency representation while using standard MOSFET models that are already widely implemented and easy to manufacture.
3Measurement precision
If the gap region parasitic resistance is neglected, then the device complexity is reduced, but the measurement precision of cell current under low voltage conditions deteriorates
Solution Approach 1:
The variable resistor model is designed to dynamically adjust its resistance value based on the applied voltage conditions. Under low voltage conditions (Vsg < Vth), the gap region parasitic resistance becomes significant and the model accurately captures this effect. Under high voltage conditions, the resistance effect diminishes as expected. This dynamic behavior improves measurement precision across different operating conditions without requiring a fundamentally different model structure.
Data Source
AI summary
According to an embodiment, element models include a first transistor model, a second transistor model, and a variable resistor model. The first transistor model simulates a characteristic of a selection gate transistor whose channel resistance is changed by a selection gate voltage applied to a selection gate. The second transistor model simulates a characteristic of a memory gate transistor whose channel resistance is changed by a memory gate voltage applied to a memory gate. The variable resistor model has a resistance value which is changed in accordance with the selection gate voltage and the memory gate voltage and which is set to correspond to a gap region formed in a lower part of an insulating film insulating between the selection gate and the memory gate. The variable resistor model is provided between the first transistor model and the second transistor model.