Split-Gate MONOS FinFET High-Impurity P-Type Layer
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Solution Overview
Problem
The split-gate type MONOS transistor using FinFETs faces challenges in writing and erasing efficiency due to a low vertical electric field, which affects the performance of charge injection and extraction processes.
Innovation Solution
A semiconductor device with a split-gate type MONOS structure incorporating a FinFET design, featuring a p-type semiconductor layer with higher impurity concentration under the memory gate, allowing for improved writing characteristics by generating a higher electric field for efficient charge injection and extraction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a FinFET structure with double-gate is used, then the short channel effect is suppressed and impurity concentration can be kept low, but the vertical electric field becomes extremely small which deteriorates writing and erasing efficiency
Solution Approach 1:
The patent introduces a p-type semiconductor layer with high impurity concentration specifically under the memory gate region, creating a localized area with enhanced electric field generation capability. This local modification allows the vertical electric field to be increased in the charge trapping region without affecting the overall low impurity concentration in the channel, thus resolving the contradiction between maintaining low short channel effect and achieving high writing/erasing efficiency
2Reliability
If the impurity concentration of the channel is increased to suppress short channel effect, then the potential distribution becomes steep, but the vertical electric field increases which may affect the flat potential distribution characteristic of FinFET
Solution Approach 1:
The p-type semiconductor layer is positioned only under the memory gate where charge trapping occurs, not throughout the entire channel. This localized high impurity concentration region generates the necessary vertical electric field for efficient charge injection and extraction while preserving the flat potential distribution in the main channel region, thus resolving the contradiction between short channel effect suppression and maintaining flat potential distribution
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The enhanced electric field in the channel region improves writing efficiency and reduces noise, leading to better performance in charge trapping and retrieval operations.
Implementation Method 1
the charge injection and the charge extraction to and from the charge retaining portion are performed by using the vertical electric field at the time of writing and erasing
Implementation Method 2
a p-type semiconductor layer which is formed under the second channel forming layer and has an impurity concentration higher than an impurity concentration of a semiconductor substrate
Data Source
AI summary
A semiconductor device has a split-gate type MONOS structure using a FinFET, and it includes a source and a drain each formed of an n-type impurity diffusion layer, a first channel forming layer which is formed under a control gate and is formed of a semiconductor layer doped with a p-type impurity, and a second channel forming layer which is formed under a memory gate and is formed of a semiconductor layer doped with an n-type impurity. Further, the semiconductor device includes a p-type semiconductor layer which is formed under the second channel forming layer and has an impurity concentration higher than an impurity concentration of a semiconductor substrate.