MONOS Memory Gate Double-Gate Structure for Erase Speed
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Solution Overview
Problem
The existing Fowler Nordheim (FN) tunnel method for erasing data in MONOS-type nonvolatile memory cells has low erase speed and cannot reduce the threshold voltage to desired levels, limiting the performance of semiconductor devices with embedded nonvolatile memory.
Innovation Solution
A semiconductor device configuration with a double-gate structure, featuring a selection gate and two memory gates with specific insulating films and gate electrodes, allows for efficient hole injection during the erase operation by concentrating electric fields on the corner portions of the memory gate electrodes, enhancing erase speed and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the Fowler Nordheim tunnel method is used for erasing data in MONOS-type nonvolatile memory cells, then the memory cell structure is simple, but the erase speed is low and the threshold voltage cannot be reduced to desired levels
Solution Approach 1:
The memory gate is divided into two separate gates (first memory gate and second memory gate), each capable of independently injecting holes into the charge storage film. This segmentation allows parallel erase operations and significantly improves erase speed while maintaining a relatively simple overall structure
Solution Approach 2:
The patent introduces a dual-gate configuration where the second memory gate is positioned on the opposite side of the charge storage film relative to the first memory gate. This spatial arrangement in another dimension enables simultaneous hole injection from both sides, dramatically enhancing erase efficiency
2Manufacturing precision
If the Fowler Nordheim tunnel method is used for erasing data, then the manufacturing process is simple, but the threshold voltage cannot be reduced to desired levels
Solution Approach 1:
The patent employs different insulating film materials for the two memory gates (nitride film for the first gate, oxide film for the second gate), allowing independent control of hole injection characteristics. This parameter differentiation enables precise threshold voltage control during erase operations while using standard semiconductor manufacturing processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The double-gate structure improves erase speed and efficiency, allowing for faster data erasure and improved performance of semiconductor devices with embedded nonvolatile memory cells.
Implementation Method 1
The existing Fowler Nordheim (FN) tunnel method for erasing data in MONOS-type nonvolatile memory cells has low erase speed
Data Source
AI summary
A memory gate is formed of a first memory gate including a second gate insulating film made of a second insulating film and a first memory gate electrode, and a second memory gate including a third gate insulating film made of a third insulating film and a second memory gate electrode. In addition, the lower surface of the second memory gate electrode is located lower in level than the lower surface of the first memory gate electrode. As a result, during an erase operation, an electric field is concentrated on the corner portion of the first memory gate electrode which is located closer to a selection gate and a semiconductor substrate and on the corner portion of the second memory gate electrode which is located closer to the first memory gate and the semiconductor substrate. This allows easy injection of holes into each of the second and third insulating films.