MONOS Sense Amplifier Reference Circuit for Flash Memory Timing
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Solution Overview
Problem
In flash memory devices, the difference in capacitance, resistance, and current path between the read target memory cell and the reference cell selection transistor leads to timing deviations in sense amplifier discharge, causing erroneous reading.
Innovation Solution
The implementation of a non-volatile semiconductor memory device with a sense amplifier connected to first and second bit lines, a MONOS type memory cell column, a constant current source, and a switch formed by a MONOS type transistor, ensuring both the memory cell column and the switch are formed by MONOS type transistors to reduce erroneous reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a latch type sense amplifier is used with a reference cell selection transistor to enable low power consumption and low voltage operation, then power consumption is reduced, but timing deviation occurs between sense amplifier terminals causing erroneous reading
Solution Approach 1:
The patent applies homogeneity by making both the reference cell selection transistor and the read target memory cell transistor MONOS type transistors. This ensures they have identical capacitance, resistance, and current path characteristics, eliminating timing deviation during discharge while maintaining the low power consumption benefits of the latch type sense amplifier structure.
2Ease of operation
If a reference cell selection transistor is used to switch the sense amplifier and reference cell to conduction state, then reading operation is enabled, but timing deviation occurs due to difference in capacitance and resistance between the reference cell selection transistor and read target memory cell
Solution Approach 1:
The patent uses MONOS type transistors for both the reference cell selection transistor and read target memory cell to ensure identical electrical characteristics. This homogeneity in transistor type, structure, and parameters ensures synchronized discharge timing while maintaining the ability to perform reading operations through the reference cell selection mechanism.
3Device complexity
If different transistor types are used for reference cell selection and memory cell, then device complexity is reduced, but timing deviation occurs causing erroneous reading
Solution Approach 1:
The patent specifies that both the reference cell selection transistor and read target memory cell transistor shall be MONOS type transistors with identical structure and electrical characteristics. This homogeneity approach ensures timing synchronization during discharge while maintaining relatively simple device structure, as both transistor types are the same and can be fabricated using the same process.
Data Source
AI summary
A non-volatile semiconductor memory device includes a sense amplifier, first and second bit lines that are connected to the sense amplifier, a first memory cell column that is connected to the first bit line, the first memory cell column being formed by a plurality of MONOS type transistors, a first constant current source that is connected to the second bit line, the first constant current source generating a reference current for the first memory cell column, and a first switch that is provided between the first constant current source and the second bit line, the first switch being formed by a MONOS type transistor.