3D Monte Carlo Random-Walk for IC Parasitic Extraction

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Solution Overview

Problem

Current methods for parasitic RLC extraction in integrated circuit design face challenges with accuracy and scalability, particularly in handling large full-chip designs due to capacity limitations and the need for manual verification, leading to design respins and performance issues.

Innovation Solution

A synergy of stochastic methods and hierarchical processing is employed, using a three-dimensional Monte Carlo random-walk process to extract coupling parameters, which allows for exact capacitance extraction and reduces redundant calculations by storing significant neighborhoods, enabling accurate and efficient handling of complex IC layouts without relying on pre-computed pattern matching.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If mesh-based TCAD tools are used for accurate RLC extraction, then extraction accuracy is improved, but the tool capacity is limited to handling only small numbers of 3D objects

Engineering Contradiction:
Improveextraction accuracyVSAvoidtool capacity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent replaces the traditional mesh-based mechanical/numerical system with a stochastic random-walk system. Instead of using finite element or boundary element methods that require space partitioning into mesh elements, the invention uses random walks of particles through the dielectric space to compute capacitance. This substitution allows handling of large-scale IC designs with millions of conductors while maintaining accuracy, as the random-walk approach has linear computational complexity rather than super-linear complexity.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Device complexity

If pattern-matching based extraction tools are used for large full-chip designs, then tool capacity is improved, but extraction accuracy deteriorates due to approximations and ignored effects

Engineering Contradiction:
Improvetool capacityVSAvoidextraction accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent replaces the pattern-matching approach with a fundamental stochastic simulation method. Instead of approximating complex IC layouts by matching them to pre-solved patterns in a library, the invention directly simulates the physical random-walk process in the actual dielectric space. This eliminates the need for pattern libraries and approximations, providing both full-chip capacity and accurate extraction of coupling effects including fringing and interline coupling.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Measurement precision

If manual verification processes are used for critical nets, then extraction accuracy is improved, but productivity deteriorates due to tedious manual selection and verification

Engineering Contradiction:
Improveextraction accuracyVSAvoidverification efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent implements a self-verifying extraction system where the stochastic random-walk method inherently provides accurate results for all nets simultaneously without requiring manual selection or verification. The random-walk simulation naturally captures all coupling effects for every conductor in the design, eliminating the need for manual identification of critical nets and subsequent verification steps. This self-service approach maintains accuracy while dramatically improving productivity for large-scale designs.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS7669152B1Three-dimensional hierarchical coupling extraction
Publication Date: 2010.02.23 SYNOPSYS INC
  • US7669152B1 patent drawing
  • US7669152B1 patent drawing
  • US7669152B1 patent drawing

AI summary

Apparatus, systems, and methods are provided for processing integrated circuit chip design. A three-dimensional Monte Carlo random-walk process may be applied to a cell in a hierarchical description of the layout of the chip to extract information regarding the cell. The information may include coupling resistance, capacitance, inductance, or combinations thereof. A neighborhood of the cell may be built and data correlated to the neighborhood may be stored. Such a technique may be applied from a bottom level to a top level of the hierarchical description of the chip layout.