Compact MOS Antenna Diode Layout for ASIC Area Reduction
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Solution Overview
Problem
The existing antenna diodes used to prevent antenna violations in MOS integrated circuits are bulky and increase the area footprint of ASICs, while also adding capacitance, which affects the reliability and yield of the manufacturing process due to plasma-induced gate dielectric damage.
Innovation Solution
A compact MOS diode design is introduced, featuring a pMOS and nMOS transistor configuration with specific interconnects and voltage sources, which reduces the antenna effect by providing improved protection without significantly increasing the area footprint or leakage current, while maintaining effective antenna protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional antenna diode is added to protect the gate dielectric, then antenna protection is improved, but the area footprint of the ASIC increases
Solution Approach 1:
The patent combines multiple transistors (first nMOS transistor, second nMOS transistor, and pMOS transistor) into a single integrated antenna diode structure. The transistors are merged such that their sources, drains, and gates are interconnected to form a compact diode equivalent circuit, reducing the overall area footprint while maintaining protection functionality.
Solution Approach 2:
The antenna diode structure serves multiple functions: it protects the gate dielectric from plasma-induced damage, provides a discharge path for accumulated charge, and can be integrated into the existing transistor layout without requiring separate dedicated protection structures. The shared source/drain regions serve both as transistor terminals and diode terminals.
2Reliability
If a traditional antenna diode is added to protect the gate dielectric, then antenna protection is improved, but the device complexity increases
Solution Approach 1:
The patent merges the antenna diode functionality with existing transistor structures. The first and second nMOS transistors share a common source region, and the pMOS transistor shares source/drain regions with the nMOS transistors. This merging reduces device complexity by eliminating redundant structures and simplifying the overall circuit architecture.
Solution Approach 2:
The antenna diode is segmented into multiple transistor components (first nMOS, second nMOS, pMOS) that can be independently designed and optimized, yet function together as a unified protection structure. This segmentation allows for modular design and easier integration into existing CMOS processes.
3Reliability
If the antenna diode protection structure is expanded to increase protection area, then antenna protection is improved, but the area footprint increases
Solution Approach 1:
The patent nests the antenna diode structure within the existing transistor layout. The first and second nMOS transistors are positioned adjacent to each other sharing a common source, and the pMOS transistor is integrated with shared source/drain regions. This nesting arrangement maximizes protection area within the available footprint by utilizing overlapping and shared structural elements.
Solution Approach 2:
The patent utilizes vertical stacking and three-dimensional integration of the transistor structures. The shared source/drain regions extend in multiple dimensions, and the gate structures are positioned at different vertical levels, effectively increasing the protection area without proportionally increasing the planar footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The compact antenna diode design provides 37% greater protection area and 50% reduced footprint compared to previous designs, with minimal impact on leakage current and input capacitance, thus enhancing the reliability and yield of MOS integrated circuits.
Implementation Method 1
gated diode has a reduced breakdown voltage relative to the gate oxide layer of first transistor and thus establishes a leakage path to semiconductor layer to direct leakage current to semiconductor layer, thereby inhibiting charge from accumulating on the gate oxide layer of first transistor
Data Source
Figure 1A~1C
Figure 2
Figure 3
AI summary
A MOS device for reducing an antenna effect is provided. The MOS device includes a diode including a first nMOS transistor having a first nMOS transistor source, a first nMOS transistor drain, a first nMOS transistor gate, and an nMOS transistor body. The nMOS transistor body is coupled to a first voltage source and is an anode of the diode. The first nMOS transistor source, the first nMOS transistor drain, and the first nMOS transistor gate are coupled together and are a cathode of the diode. The MOS device further includes an interconnect extending between a driver output and a load input. The interconnect is coupled to the cathode of the diode. The interconnect may extend on one metal layer only between the driver output and the load input.