Dynamic Bias Voltage Circuit for MOS Gate-Drain Voltage Protection
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Solution Overview
Problem
Existing dynamic bias voltage circuits for integrated circuits struggle to reliably manage wide voltage variation ranges on USB IC signal pads, potentially exceeding the maximum withstand voltage of MOS transistors.
Innovation Solution
A dynamic bias voltage circuit comprising a buffer circuit, a voltage divider circuit, and a voltage follower circuit, which dynamically tracks voltage variations on IC pads to ensure the absolute value of gate-to-drain voltages of MOS transistors does not exceed the maximum withstand voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a static bias voltage is set at the gate of MOS transistors, then the circuit operation is simplified, but the gate-to-drain voltage may exceed the maximum withstand voltage under wide pad voltage variations
Solution Approach 1:
The patent implements a dynamic bias voltage circuit that automatically adjusts the gate bias voltage according to the pad voltage level. The circuit uses voltage followers and voltage dividers to generate a bias voltage that dynamically tracks the pad voltage, ensuring the gate-to-drain voltage remains within safe limits throughout the operating range, thus resolving the contradiction between circuit simplicity and reliability.
2Reliability
If the bias voltage dynamically tracks pad voltage variations, then the transistor reliability is improved, but the circuit complexity increases
Solution Approach 1:
The patent introduces intermediary circuits (voltage followers and voltage dividers) that mediate between the pad voltage and the gate bias voltage. These intermediary components transform the wide pad voltage range into a controlled bias voltage range, providing reliability protection while maintaining reasonable circuit complexity through standard analog building blocks.
3Reliability
If the gate bias voltage is set to protect against maximum pad voltage, then transistor reliability is improved, but the transistor may not operate in saturation region under minimum pad voltage
Solution Approach 1:
The patent employs parameter changes by dynamically adjusting the gate bias voltage according to the instantaneous pad voltage level. The bias voltage is proportionally scaled to match the pad voltage, ensuring that the gate-to-drain voltage maintains an appropriate relationship regardless of the operating point, thus keeping transistors in saturation region across the full voltage range while maintaining reliability.
Data Source
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AI summary
A dynamic bias voltage circuit (100) for providing a bias voltage (VP) includes: a buffer circuit (110), a voltage divider circuit (120) and a voltage follower circuit (130). The buffer circuit (110) is configured to output a second voltage (V2) according to a first voltage (V1). The voltage divider circuit (120) is coupled to the buffer circuit (110) and configured to implement a voltage division function to provide a third voltage (V3) according to the second voltage (V2) and a pad voltage (V_PAD) on a pad (PAD) of the integrated circuit (100). The voltage follower circuit (130) is coupled to the voltage divider circuit (120) and configured to generate the bias voltage (VP) according to the third voltage (V3).