MOS Decoupling Capacitor Well Ties and High-Dose Implant
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Solution Overview
Problem
Traditional decoupling capacitor designs in semiconductor components face issues such as leakage current, latch-up, and the well proximity effect, which affect the performance and regularity of logic circuits, particularly when integrated into standard cell rows.
Innovation Solution
The design incorporates a pair of metal-oxide-semiconductor (MOS) capacitors formed in wells of opposite polarity with high-dose implants and asymmetrical well-ties, using additional conductive and insulating materials like polycrystalline silicon and silicon nitride, to improve decoupling and reduce variations in the well proximity effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the ground node is connected to a lightly- or moderately-doped N-well to improve high-frequency response, then high-frequency response is improved, but leakage current and latch-up occur
Solution Approach 1:
The patent changes the doping concentration parameter of the N-well from lightly- or moderately-doped to heavily-doped. This parameter change simultaneously improves high-frequency response by reducing N-well resistance and prevents leakage current and latch-up by eliminating the conditions that cause these failures in lightly-doped wells.
Solution Approach 2:
The patent applies a high-dose implant to the N-well region before forming the decoupling capacitor structure. This preliminary doping action ensures that the N-well has sufficiently high doping concentration to prevent latch-up and leakage current while maintaining low resistance for high-frequency performance.
2Reliability
If a space is required between the logic N-well and the decap N-well to prevent leakage current, then leakage current is prevented, but the decap cannot be placed close to surrounding logic
Solution Approach 1:
By changing the N-well doping concentration to heavily-doped, the patent eliminates the need for spacing between logic N-wells and decap N-wells. The high doping concentration prevents leakage current and latch-up internally, allowing adjacent wells to be placed directly next to each other without requiring additional spacing for protection.
3Productivity
If the decap structure is placed close to surrounding logic, then decoupling efficiency is improved, but the N-well shape is altered and regular pattern is interrupted
Solution Approach 1:
The heavily-doped N-well allows the decap structure to be integrated within standard cell rows without altering N-well shapes or interrupting the regular pattern. The high doping concentration provides inherent protection against leakage and latch-up, enabling close placement of decaps to logic regions while maintaining both the regular N-well pattern and high decoupling efficiency.
4Area of stationary object
If logic transistors are placed close to the edge of the N-well, then area is reduced, but the well proximity effect causes undesirable variation
Solution Approach 1:
By heavily-doping the N-well, the patent reduces the well proximity effect that causes transistor parameter variations. The high doping concentration changes the electrical characteristics of the N-well, allowing logic transistors to be placed closer to the N-well edge while maintaining consistent transistor parameters across the circuit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances high-frequency response, reduces series resistance, and minimizes the well proximity effect, allowing for closer placement of decaps to logic regions without disrupting the standard cell pattern, thereby improving decoupling efficiency and circuit performance.
Implementation Method 1
forming a first high-dose implant within the first well region; forming a second high-dose implant within the second well region; wherein the first high-dose implant and the second high-dose implant each have an active surface dopant concentration of at least 1E19/cm³
Implementation Method 2
a pair of metal-oxide-semiconductor (MOS) capacitors formed in wells of opposite plurality
Data Source
Figure 1
Figure 2~3
Figure 4~5
AI summary
A decoupling capacitor includes a pair of MOS capacitors (106,108) formed in wells (102,104) of opposite plurality. Each MOS capacitor has a set of well -ties and a high-dose implant, (110,112,114,116) allowing high frequency performance under accumulation or depletion biasing. The top conductor of each MOS capacitor is electrically coupled to the well -ties of the other MOS capacitor and biased consistently with logic transistor wells. The well-ties and/or the high-dose implants of the MOS capacitors exhibit asymmetry with respect to their dopant polarities.