MOS Transistor Embedded Substrate with Opposite Mounting Directions
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Solution Overview
Problem
The existing packaging methods for vertical MOS transistors in IC substrates are inadequate for high-reliability applications due to insufficient mechanical strength, high electrical resistance, and poor heat radiation properties, and the wiring layout becomes complex when connecting multiple transistors for switching power supplies.
Innovation Solution
A MOS transistor embedded substrate design where first and second MOS transistors are embedded with opposite mounting directions, allowing for simplified wiring patterns and improved connectivity through insulation resin layers and via conductors, reducing connection resistance and enhancing mechanical strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vertical MOS transistors are connected using conductive paste, solder, bonding wire or lead frame, then the transistors can be electrically connected, but the mechanical strength of the connection part is insufficient and the electrical resistance is high
Solution Approach 1:
The patent merges the connection function with the substrate structure by embedding MOS transistors directly into the substrate and using internal wiring patterns and via conductors to connect them. This eliminates the need for separate connection materials like conductive paste, solder, and bonding wires, thereby improving both mechanical strength and electrical conductivity simultaneously.
Solution Approach 2:
The substrate acts as an intermediary structure that provides direct electrical connection paths between MOS transistors through integrated wiring patterns and via conductors. This intermediary structure replaces traditional connection materials and provides both mechanical support and electrical connectivity with superior performance.
2Ease of manufacture
If two MOS transistors are disposed side by side inside the substrate with conventional wiring, then the transistors can be connected, but the layout of the wiring pattern becomes complicated
Solution Approach 1:
The patent employs asymmetric arrangement of MOS transistors with opposite orientations (first transistor with source facing up, second transistor with source facing down). This asymmetric configuration, combined with strategic placement of via conductors, simplifies the wiring pattern by reducing the number of required connection paths and making the layout more regular and manufacturable.
Solution Approach 2:
The patent utilizes the third dimension (vertical depth) by embedding transistors at different depths and using via conductors to connect different layers. This dimensional approach allows for simplified surface wiring patterns while achieving the necessary electrical connections through the substrate depth, thereby reducing overall wiring complexity.
Data Source
AI summary
Disclosed herein is a MOS transistor embedded substrate that includes first and second MOS transistors each having a source electrode formed on one surface and a drain electrode formed on other surface, and an insulation resin layer in which the first and second MOS transistors are embedded such that the source electrode of the first MOS transistor and the drain electrode of the second MOS transistor face a same direction and that the drain electrode of the first MOS transistor and the source electrode of the second MOS transistor face a same direction.