Vertical MOS Transistor Gate Trench Layout for Lower On-Resistance
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Solution Overview
Problem
There is a demand for reducing the on-resistance of semiconductor devices that include a vertical MOS transistor and a peripheral element, as existing methods face challenges in minimizing on-resistance while maintaining breakdown voltage and preventing parasitic bipolar transistor activation.
Innovation Solution
A manufacturing method for a face-down mountable, chip-size-package semiconductor device involves forming a semiconductor layer with a vertical MOS transistor and a peripheral element, where gate trenches and grooves are strategically created and filled with polysilicon, and the structure is polished to ensure flush surfaces, reducing the mesa width and source region width, thereby minimizing on-resistance and preventing parasitic bipolar transistor activation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the on-resistance of the vertical MOS transistor is reduced by optimizing the semiconductor layer structure, then the electrical performance is improved, but the manufacturing precision requirements increase due to the need for precise gate trench formation and polysilicon deposition
Solution Approach 1:
The patent applies preliminary action by forming the gate trenches to a predetermined depth before polysilicon deposition, and by controlling the deposition process to achieve the exact required polysilicon thickness. This sequential preparation ensures that when the transistor is completed, the on-resistance is optimized without requiring post-manufacturing adjustments.
Solution Approach 2:
The patent utilizes parameter changes by precisely controlling the gate trench depth, polysilicon deposition thickness, and impurity injection parameters to achieve the desired on-resistance value. By adjusting these physical parameters during manufacturing, the electrical characteristics of the transistor are optimized while maintaining manufacturing feasibility.
2Reliability
If multiple processes are used to form the peripheral element with precise thickness control, then the device performance is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent merges multiple manufacturing operations into integrated process steps. For example, the gate trench formation is combined with subsequent polysilicon deposition in a sequential flow without intermediate handling, and the impurity injection for the peripheral element is integrated into the same manufacturing cycle. This reduces manufacturing complexity while maintaining precise thickness control and device performance.
Solution Approach 2:
The manufacturing process exhibits universality by using the same polysilicon deposition and impurity injection techniques for both the vertical MOS transistor and the peripheral element. This multi-functional approach allows a single set of manufacturing tools and processes to create different device components with consistent quality, reducing overall manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces the on-resistance of the vertical MOS transistor while maintaining a high breakdown voltage, allowing for a semiconductor device with improved performance and reduced parasitic bipolar transistor activation.
Implementation Method 1
making a thickness of the peripheral element equal to the depth h by concurrently removing the polysilicon deposited in the plurality of gate trenches and the polysilicon deposited in the second groove by chemical mechanical polishing
Implementation Method 2
depositing a first oxide film up to at least the upper surface of the semiconductor layer to fill the first groove, and concurrently forming a second oxide film of a thickness a on the upper surface of the semiconductor layer
Data Source
AI summary
A semiconductor device manufacturing method includes: forming a first groove having depth H in a semiconductor layer; filling the first groove with an oxide film and forming a surface oxide film having thickness a on an upper surface of the semiconductor layer to equalize the oxide film and the surface oxide film in height; forming a second groove having depth h greater than thickness a, from an uppermost surface of a third oxide film; forming gate trenches deeper than depth H, in the semiconductor layer; depositing polysilicon until at least the gate trenches and the second groove are filled with polysilicon;forming a peripheral element by injecting an impurity into polysilicon deposited in the second groove; and making a thickness of the peripheral element equal to depth h by concurrently removing polysilicon deposited in the gate trenches and polysilicon deposited in the second groove until they become equal in height.