MOS Transistor Hump Effect Prevention via Edge Insulation
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Solution Overview
Problem
High-voltage semiconductor power ICs face performance reduction due to the 'Hump effect' caused by parasitic MOS transistors formed near the edge of the gate, leading to increased off-state current in real MOS transistors.
Innovation Solution
The MOS transistor structure incorporates heavily doped regions and insulators in the active area to prevent the formation of parasitic MOS transistors, either by spacing them apart or partially covering the source and drain regions with insulators, thereby eliminating or mitigating the Hump effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate insulator thickness is reduced near the gate edge to improve transistor performance, then the threshold voltage of parasitic MOS transistors decreases, but the Hump effect increases and off-state current increases
Solution Approach 1:
The invention extracts and removes the harmful parasitic MOS transistors from the system by filling the region near the gate edge with insulating material, thereby eliminating the source of the Hump effect while preserving the beneficial thin gate insulator region for the main transistor channel
Solution Approach 2:
The invention applies different gate insulator thicknesses in different regions: a thin gate insulator under the main channel for high performance, and a thick gate insulator (filled with insulating material) at the gate edge to prevent parasitic transistor formation, thereby achieving local optimization of both performance and reliability
2Object-generated harmful factors
If heavily doped regions are added to prevent parasitic MOS transistors, then the Hump effect is reduced, but the device structure becomes more complex
Solution Approach 1:
The invention changes the physical state and properties of the gate insulator region by filling it with insulating material, transforming it from an active transistor region to an inactive insulating region, thereby preventing parasitic transistor formation through material property modification rather than adding separate structural elements
Solution Approach 2:
The insulating material filling serves multiple functions: it prevents parasitic MOS transistor formation, maintains the thin gate insulator profile for the main channel, and provides mechanical support, thereby achieving multiple benefits through a single structural feature
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the performance of power ICs by reducing the Hump effect, without increasing manufacturing steps or costs, as the heavily doped regions and insulators effectively prevent the formation of parasitic transistors, thus enhancing the transistor's characteristics.
Implementation Method 1
first and second heavily doped regions of a second conductivity type in the active area adjacent to the first and second edges thereof
Implementation Method 2
first and second insulators in the active area adjacent to the first and second edges thereof, respectively, and spaced apart from each other by the source region
Data Source
AI summary
A MOS transistor structure is provided. The MOS transistor structure includes a semiconductor substrate having an active area including a first edge and a second edge opposite thereto. A gate layer is disposed on the active area of the semiconductor substrate and has a first edge extending across the first and second edges of the active area. A source region having a first conductivity type is in the active area at a side of the first edge of the gate layer and between the first and second edges of the active area. First and second heavily doped regions of a second conductivity type are in the active area adjacent to the first and second edges thereof, respectively, and spaced apart from each other by the source region.