MOS Field Plate Trench Transistor Mesa Width Optimization
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Solution Overview
Problem
Modern MOS transistors face challenges in reducing area-specific on resistance (Ron·A) to minimize static power loss and achieve higher current densities, while maintaining reliable avalanche breakdown properties, as existing methods either compromise on space or deteriorate the figure of merit (FOM) due to limitations in mesa width and breakdown location.
Innovation Solution
The MOS field plate trench transistor device incorporates a mesa region with a body contact hole, where the mesa width is adjusted to be within 1.5 times the trench width, allowing the avalanche breakdown region to be shifted to the trench bottom, thereby increasing breakdown voltage and reducing on resistance without compromising body contact space or FOM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the mesa width is reduced to increase integration density, then the area-specific on resistance decreases, but the body contact hole space becomes insufficient
Solution Approach 1:
The patent applies parameter changes by precisely controlling the mesa width within a specific range (0.5×trench width to 1.5×trench width) to simultaneously achieve low on resistance and sufficient body contact hole space. This quantitative parameter optimization resolves the contradiction between minimizing energy loss and maintaining adequate contact area.
2Reliability
If the avalanche breakdown region is shifted to the trench bottom, then the breakdown voltage increases, but the mesa width must be precisely controlled which increases manufacturing complexity
Solution Approach 1:
The patent defines a specific parameter range for mesa width (0.5×trench width to 1.5×trench width) that ensures the avalanche breakdown region forms at the trench bottom. This parameter specification balances the need for high breakdown voltage with manufacturable precision requirements.
Solution Approach 2:
The patent performs preliminary design of the mesa width based on the trench width before manufacturing, calculating the optimal range to pre-establish the avalanche breakdown region position. This preliminary action guides the manufacturing process and reduces the actual manufacturing complexity.
3Loss of energy
If deep trench structures are used to reduce drift path resistance, then the channel resistance decreases, but the device complexity increases
Solution Approach 1:
The patent segments the device structure into distinct regions: the deep trench structure for drift path optimization, the mesa region for current flow control, and the body contact hole region for electrical connection. This segmentation allows each region to be optimized independently, reducing overall device complexity while maintaining low drift path resistance.
Data Source
AI summary
A MOS field plate trench transistor device is disclosed. In one embodiment, in order to obtain a lowest possible on resistance, in the case of a MOS field plate trench transistor device having a body contact hole, it is proposed to form the avalanche breakdown region preferably in an end region of a provided trench structure by virtue of the fact that a mesa region with the body contact region in the semiconductor region as intermediate region in a direction running perpendicular to the first direction and with respect to an adjacent MOS transistor device has a width DMesa, the value of which corresponds to the value of the width DTrench of the trench structure in this direction or exceeds said value and does not go beyond 1.5 times said value, so that the following holds true: DTrench≦DMesa≦1.5·DTrench. As an alternative, the width DMesa is chosen such that the body contact hole precisely still has space, but the breakdown region is in any event shifted into the end region.