Trench MOSFET Protective Contact Acute Triangle Layout
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Solution Overview
Problem
In semiconductor devices, particularly trench-gate MOSFETs, the arrangement of protective contact regions affects both on-resistance and short-circuit withstand capability, with a trade-off between reducing on-resistance and improving short-circuit withstand, as the distance between protective contact regions and diffusion layers influences the concentration of short-circuit current.
Innovation Solution
The semiconductor device incorporates a substrate with a drift layer, base region, source region, trench, protective diffusion layer, gate insulating film, gate electrode, source electrode, and protective contact regions arranged in an acute triangle pattern to minimize the distance between protective contact regions, thereby enhancing short-circuit withstand capability while controlling on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If protective contact regions are arranged in a lattice pattern with larger spacing, then on-resistance decreases, but short-circuit withstand capability deteriorates
Solution Approach 1:
The patent applies asymmetry by transitioning from a symmetric lattice pattern to an asymmetric acute triangle pattern for arranging protective contact regions. This asymmetric arrangement optimizes the spatial distribution to simultaneously reduce on-resistance and improve short-circuit withstand capability by ensuring more uniform current density distribution during short-circuit conditions while maintaining adequate channel density.
Solution Approach 2:
The patent employs dimensionality change by considering the two-dimensional spatial arrangement of protective contact regions and optimizing their positions based on triangular geometry principles. By arranging regions at vertices of acute triangles rather than simple lattice points, the invention effectively utilizes spatial dimensions to achieve both low on-resistance and high short-circuit withstand capability.
2Reliability
If protective contact regions are arranged closer together, then short-circuit withstand capability improves, but on-resistance increases
Solution Approach 1:
The patent applies local quality by creating different functional zones through the acute triangle arrangement of protective contact regions. The arrangement ensures that regions closer to the trench receive appropriate protective function while maintaining channel density in other areas, thus locally optimizing both short-circuit protection and on-resistance characteristics without uniform compromise across the entire device.
3Loss of energy
If fewer protective contact regions are used, then on-resistance decreases, but short-circuit withstand capability deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-positioning protective contact regions at optimal locations forming acute triangles before short-circuit conditions occur. This preliminary strategic placement ensures that when short-circuit current flows, the protective regions are already in positions that maximize current distribution and minimize local concentration, thereby achieving both low on-resistance and high short-circuit withstand capability with fewer regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This arrangement improves short-circuit withstand capability by reducing the distance to the farthest protective contact region, mitigating local current concentration and breakdown, while maintaining a balance with on-resistance, thus enhancing the reliability of the semiconductor device.
Implementation Method 1
extending a depletion layer in a drift layer of first conductivity type on the bottom of the trench to provide, on the bottom of the trench, a protective diffusion layer of second conductivity type that can reduce an electric field to be applied to the insulating film on the bottom of the trench
Implementation Method 2
During the off state of the semiconductor device, an electric field tends to concentrate on an insulating film on the bottom of a trench in the trench MOSFET, on which, the reliability of the insulating film is low
Data Source
AI summary
A semiconductor device includes a base region of second conductivity type formed on a drift layer of first conductivity type, a source region of first conductivity type located in the base region, a trench passing through the base region and the source region and dividing cell regions in plan view, a protective diffusion layer of second conductivity type disposed on a bottom of the trench, a gate electrode embedded in the trench with a gate insulating film therebetween, a source electrode electrically connected to the source region, and a protective contact region disposed at each of positions of three or more cell regions and connecting the protective diffusion layer and the source electrode to each other. The protective contact regions are disposed such that a triangle whose vertices are centers of three protective contact regions located closest to one another is an acute triangle.