MOSFET Bulk Voltage Control for Low-Leakage Sample and Hold
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Solution Overview
Problem
Sample and hold stages with MOS transistors suffer from significant leakage currents due to bulk-source diode leakage, which existing solutions fail to adequately address without compromising switching speed or capacitor size constraints.
Innovation Solution
The bulk of the MOS transistor is controlled to have a voltage level equal to the input node of the voltage follower, minimizing the voltage drop across the transistor, and additional switches and a control stage are used to manage the switching and settling of the operational amplifier to prevent glitches and leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the MOS transistor bulk is connected to the substrate, then the device complexity is reduced, but the leakage current increases significantly
Solution Approach 1:
The bulk connection is segmented into multiple independent nodes (first bulk node and second bulk node) that can be independently controlled. This allows different voltage levels to be applied to different parts of the bulk, enabling precise control of the potential distribution to minimize leakage current while maintaining manageable device complexity.
Solution Approach 2:
An intermediate potential distribution is introduced between the substrate and the bulk through controlled voltage application to the bulk nodes. This intermediate potential layer acts as a mediator that reduces the direct voltage drop across the bulk-source junction, thereby minimizing leakage current while keeping the overall structure relatively simple.
2Object-generated harmful factors
If the voltage drop across the MOS transistor is reduced, then the leakage current decreases, but the control complexity increases
Solution Approach 1:
The bulk voltage is preliminarily adjusted to an intermediate level before the switching operation occurs. By pre-establishing the appropriate potential distribution in the bulk, the transistor is prepared to operate with minimal voltage drop and leakage current from the outset, reducing the need for complex real-time control mechanisms.
Solution Approach 2:
The bulk voltage control is made dynamic, allowing the bulk nodes to switch between different voltage levels (intermediate level during hold phase, different level during sample phase). This dynamic adjustment enables the system to optimize leakage reduction during critical operations while maintaining flexibility for other operational requirements.
3Object-generated harmful factors
If additional switches and control stages are added, then the leakage current is reduced, but the device complexity increases
Solution Approach 1:
The additional switches and control stages are designed to perform multiple functions: they control the bulk voltage for leakage reduction, manage the sampling and holding operations, and coordinate the timing of various circuit elements. By making these components multi-functional, the increase in device complexity is justified by the multiple benefits achieved rather than single-purpose additions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces leakage currents to near zero, ensuring accurate voltage holding and fast sampling operations without compromising switching speed or increasing capacitor size.
Implementation Method 1
The bulk of the MOS transistor is controlled, such that the voltage drop between the bulk and the source or the drain of the MOS transistor is reduced. For a small voltage drop across the MOS transistor, only a very small leakage current is to be expected.
Implementation Method 2
A sampling capacitor and a plurality of switches. An input switch connects one side of the sampling capacitor to an input voltage. After this sampling phase the input switch opens and the charge on the sampling capacitor is frozen. The voltage level on the sampling capacitor is maintained during the hold phase
Data Source
AI summary
An integrated electronic device includes a sample and hold stage. The sample and hold stage has a sampling capacitor (C) for an input voltage at an input node (Vin), a first switch (S1) coupled between the input node (Vin) and the sampling capacitor (C) for connecting the input node (Vin) to the sampling capacitor (C). There is also a voltage follower with an input coupled to the sampling capacitor (C). The first switch (S1) includes a first MOS transistor (NM1) coupled between the input node (Vin) and the sampling capacitor (C). The first MOS transistor has a bulk. The sample and hold stage is adapted to selectively couple the bulk to a node having a voltage level (V3) which is equal or close to the voltage level at the input node of the voltage follower.