MOSFET Clamp Circuit for Thin-Oxide Voltage Regulator Output Stages

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Solution Overview

Problem

MOSFET transistors used in high current and voltage applications face a trade-off between size and performance, as large channel widths for low output impedance increase area consumption and gate capacitance, while thin gate insulation for smaller size limits voltage handling and speeds.

Innovation Solution

A voltage regulator output driver with a clamp circuit that uses an NMOS clamp transistor to limit the gate-to-source voltage, combined with a reference voltage generator circuit to maintain a stable clamp reference voltage, allowing for a thin gate insulation layer and minimizing area consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If the channel width is increased to reduce output impedance, then the drive capability is improved, but the transistor area and gate capacitance increase

Engineering Contradiction:
Improvedrive capabilityVSAvoidtransistor area
Core Design Contradiction:
PowerVSArea of stationary object

Solution Approach 1:

The patent applies different gate insulation thicknesses to different regions of the transistor. Specifically, the first region (under the gate electrode) has a first gate insulation thickness optimized for drive capability, while the second region (at the gate edge) has a second gate insulation thickness optimized for voltage breakdown protection. This local differentiation allows the transistor to achieve high drive capability with smaller area while maintaining voltage handling capability.

Inventive Principle:
Principle #3Local quality

2Reliability

If the gate insulation thickness is increased to handle higher voltages, then the voltage breakdown resistance is improved, but the drive capability and operating speed deteriorate

Engineering Contradiction:
Improvevoltage breakdown resistanceVSAvoiddrive capability
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

The patent implements a non-uniform gate insulation structure where the thickness varies across different regions. The first region has a thinner gate insulation layer for optimal drive capability, while the second region has a thicker gate insulation layer for enhanced voltage breakdown resistance. This resolves the contradiction by providing both thin and thick regions in the same transistor structure.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent resolves the contradiction by transitioning from a one-dimensional (uniform thickness) to a two-dimensional (varying thickness across the gate width) gate insulation structure. This dimensional change allows simultaneous optimization of drive capability (in the center region) and voltage breakdown resistance (at the edge regions).

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If the channel length is increased to improve voltage handling, then the breakdown voltage capability is improved, but the transistor area and operating speed worsen

Engineering Contradiction:
Improvebreakdown voltage capabilityVSAvoidoperating speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent applies enhanced gate insulation thickness specifically at the gate edge region where voltage breakdown is most likely to occur, rather than uniformly increasing the insulation throughout. This localized approach provides voltage breakdown protection without significantly increasing the channel length or reducing operating speed.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively protects MOSFET transistors from over-stressing, maintains low gate capacitance, and ensures stable voltage regulation despite process and temperature variations, enhancing the performance and reliability of semiconductor devices.

Implementation Method 1

A clamp circuit is coupled to the gate and limits a gate-to-source voltage of the MOSFET transistor to a level that prevents damage to a gate insulation layer of the MOSFET transistor

Methodology Applied
Scientific EffectVoltage clamping:

Implementation Method 2

A MOSFET transistor is provided that includes a first region, a second region, and a gate electrode... the MOSFET transistor consumes a relatively small amount of area and provides a low gate capacitance

Methodology Applied
Scientific EffectCapacitance reduction: Capacitance

Data Source

PatentUS20100188921A1Voltage protection circuit for thin oxide transistors, and memory device and processor-based system using same
Publication Date: 2010.07.29 MICRON TECHNOLOGY INC
  • US20100188921A1 patent drawing
  • US20100188921A1 patent drawing
  • US20100188921A1 patent drawing

AI summary

Devices, reference voltage generators, systems and methods are disclosed, including an embodiment of a voltage regulator output transistor using a thin gate insulator to provide a low output impedance despite having a semiconductor channel width that is relatively small. The output transistor is protected from damage by a clamping circuit provided to limit the gate-to-source voltage of the transistor such that damage to the output transistor should be reduced or prevented. One such clamping circuit includes a clamp transistor that receives a reference voltage at its gate. The magnitude of the reference voltage limits to voltage to which the gate of the transistor can be driven. A voltage reference circuit provides the reference voltage so that it compensates for process and temperature variations of the output transistor.