Power MOSFET Columnar Charge Balancing Decoupling
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Solution Overview
Problem
The increasing need to miniaturize power devices leads to increased packing density of transistors, which results in higher intrinsic capacitances and worsened conduction performance, especially at high switching frequencies, due to reduced distance between columns in the epitaxial layer and increased gate charge per unit surface.
Innovation Solution
A semiconductor structure with an epitaxial layer having column structures for charge balancing, where a semiconductor separating layer decouples these structures from active regions, allowing for unconstrained periodicity and improved performance by optimizing the dimensions and conductivity of the separating layer to reduce output resistance and voltage drop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the packing density of transistors is increased to miniaturize power devices, then the integration level is improved, but the intrinsic capacitances increase and conduction performance worsens
Solution Approach 1:
The invention divides the common drain layer into multiple isolated columnar structures with opposite conductivity type, creating discrete charge balancing regions. This segmentation allows the charge balancing function to be distributed throughout the drift region without requiring continuous high-doping layers that would increase capacitance between closely spaced transistors.
Solution Approach 2:
The columnar structures provide localized charge balancing at specific positions throughout the drift region, rather than requiring uniform charge distribution. This allows optimal charge balancing to be achieved locally at each transistor while maintaining low capacitance between adjacent devices through the undoped or lightly-doped regions between columns.
2Productivity
If the distance between columns in the epitaxial layer is reduced to increase transistor density, then the integration level is improved, but the conduction performance deteriorates due to increased gate charge per unit surface
Solution Approach 1:
The common drain layer is segmented into discrete columnar structures rather than a continuous layer. This segmentation allows the gate to be positioned optimally relative to each column without requiring increased gate charge, as each column independently provides charge balancing for its associated transistor channel.
Solution Approach 2:
The charge balancing function is transitioned from a two-dimensional continuous layer to a one-dimensional array of vertical columns. This dimensional change allows the columns to be spaced optimally to provide sufficient charge balancing while maintaining large enough spacing to minimize gate charge requirements, even at high transistor densities.
Data Source
AI summary
An embodiment of a semiconductor structure for a power device integrated on a semiconductor substrate, of a first type of conductivity, and comprising:—an epitaxial layer, of said first type of conductivity, made on said semiconductor substrate, and having a plurality of column structures, of a second type of conductivity, to define a charge balancing region;—an active surface layer made on said epitaxial layer for housing a plurality of active regions; said epitaxial layer comprising a semiconductor separating layer arranged between the charge balancing region and the active surface layer, said semiconductor separating layer decoupling said column structures from said active regions.