Trench MOSFET Cell Segmentation for Gate Charge Reduction
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Solution Overview
Problem
The reduction of cell pitch in trench metal-oxide-semiconductor field-effect transistors (MOSFETs) leads to increased capacitance due to larger interface areas, which negates the advantage of reduced on-resistance, resulting in slower switching speeds and higher power loss.
Innovation Solution
Incorporating a combination of conventional and diode-connected transistor cells, where the gate and source are intentionally shorted in diode-connected cells, reducing capacitance and achieving a balance between on-resistance and capacitance for enhanced MOSFET performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If cell pitch is reduced to increase cell density, then on-resistance decreases, but capacitance increases due to larger interface areas
Solution Approach 1:
The patent segments the transistor cells into two distinct types: conventional transistor cells and diode-connected transistor cells. This segmentation allows the device to simultaneously achieve low on-resistance (through high cell density with reduced pitch) and low capacitance (through the diode-connected cells that eliminate gate-to-source capacitance contribution), thereby resolving the technical contradiction between increased cell density and increased capacitance.
2Volume of moving object
If cell pitch is reduced to increase cell density, then on-resistance decreases, but switching speed decreases due to increased capacitance
Solution Approach 1:
By segmenting the transistor cells into conventional and diode-connected types, the patent enables high cell density (improving on-resistance) while the diode-connected cells specifically address the capacitance issue that limits switching speed. The diode-connected cells have their gate shorted to source, eliminating their contribution to gate-to-source capacitance, thus maintaining fast switching speeds even with reduced cell pitch.
3Volume of moving object
If cell pitch is reduced to increase cell density, then on-resistance decreases, but power loss increases due to increased capacitance
Solution Approach 1:
The patent segments the transistor population into conventional and diode-connected cells. The diode-connected cells, with their gate-source shorting, eliminate the capacitive charging/discharging losses that would otherwise occur in conventional cells. This segmentation allows the device to achieve high cell density (reduced on-resistance) while minimizing the capacitive power loss that would normally accompany reduced pitch.
Data Source
AI summary
A trench MOSFET device includes a semiconductor layer of a first doping type. MOS transistor cells are in a body region of a second doping type in the semiconductor layer. The transistor cells include a first cell type including a first trench providing a first gate electrode or the first gate electrode is on the semiconductor surface between the first trench and a second trench, and a first source region is formed in the body region. The first gate electrode is electrically isolated from the first source region. A second cell type has a third trench providing a second gate electrode or the second gate electrode is on the semiconductor surface between the third trench and a fourth trench, and a second source region is in the body region. An electrically conductive member directly connects the second gate electrode, first source region and second source region together.