MOSFET Equalizer Circuit for 0 V Center Signal Waveforms
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Solution Overview
Problem
Conventional signal waveform equalizer circuits struggle to handle input signals with a center voltage of 0 V, as used in the PCI-Express standard, and require additional circuits and restrictions, leading to increased complexity and labor in tuning circuit constants to ensure proper data reception.
Innovation Solution
The proposed signal waveform equalizer circuit uses an n-channel MOSFET with a delay circuit and a constant current source to amplify input signals, eliminating the need for a center voltage converter and allowing direct input of signals with 0 V, while also reducing the circuit scale and current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional equalizer circuits are used with center voltage 0 V input signals, then the circuit complexity increases due to additional center voltage converter circuits, but the ability to handle PCI-Express standard signals is improved
Solution Approach 1:
The patent extracts and eliminates the center voltage converter circuit from the conventional equalizer configuration. By redesigning the equalizer to directly accept center voltage 0 V input signals, the unnecessary center voltage conversion stage is removed, reducing circuit complexity while maintaining compatibility with PCI-Express standard signals.
Solution Approach 2:
The patent inverts the conventional approach by not converting the input signal to a different center voltage, but rather designing the equalizer to operate directly with the original center voltage 0 V input signals, thus eliminating the conversion step and simplifying the overall circuit.
2Reliability
If conventional equalizer circuits are used with center voltage 0 V input signals, then additional center voltage converter circuits and feedback circuits are required, but proper data reception is achieved
Solution Approach 1:
The patent removes the feedback circuit from the conventional equalizer configuration. By optimizing the delay circuit parameters and using the nMOS transistor with source input configuration, the circuit achieves proper data reception without requiring additional feedback mechanisms, thus reducing circuit scale while maintaining reliability.
Solution Approach 2:
The equalizer circuit is designed to self-adjust and achieve proper data reception through its intrinsic delay circuit characteristics and transistor configuration, eliminating the need for external feedback circuits to maintain reception accuracy.
3Adaptability or versatility
If the input signal is applied to the gate of the nMOS transistor, then the circuit can operate with sufficient current flow, but the circuit cannot handle input signals with center voltage of 0 V
Solution Approach 1:
The patent inverts the conventional signal application method by applying the input signal to the source of the nMOS transistor instead of the gate. This inversion enables the circuit to handle center voltage 0 V signals while maintaining sufficient current flow through appropriate biasing of the gate and optimization of the delay circuit.
Solution Approach 2:
The patent changes the operating parameters of the nMOS transistor by modifying which terminal receives the input signal (from gate to source) and adjusting the bias conditions, thereby enabling compatibility with center voltage 0 V signals while preserving adequate current flow for reliable operation.
4Reliability
If additional feedback circuits are added to maintain proper output voltage levels, then data reception reliability is improved, but circuit complexity and scale increase
Solution Approach 1:
The patent extracts and eliminates the feedback circuit from the equalizer configuration. By carefully designing the delay circuit time constant and the nMOS transistor bias conditions, the circuit maintains stable output voltage levels without requiring additional feedback components, thus reducing overall circuit scale while preserving reception reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient shaping of distorted waveforms without additional circuitry, allowing for higher data rates and easier data latch operation, reducing labor in tuning circuit constants and minimizing current consumption.
Implementation Method 1
an n-channel MOS field effect transistor for amplifying an input signal
Implementation Method 2
a delay circuit having a resistor connected between a drain and gate of the MOS field effect transistor and a capacitor having one terminal connected to a first node between the resistor and the gate
Data Source
AI summary
A signal waveform equalizer circuit capable of equalizing the waveform of an input signal with a center voltage of 0 V and yet small in circuit scale. An input signal (in FIG. 1, positive-phase input signal) whose waveform is to be equalized is input to the source of an nMOS, and this enables the equalizer circuit to handle an input signal with the center voltage 0 V without the need to add an extra circuit. The waveform of the input signal is shaped by a delay circuit including a resistor and a capacitor, and an output signal (in FIG. 1, positive-phase output signal) is output from a node.