Vertical Power MOSFET Field Plate Design for Capacitance Control
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Solution Overview
Problem
Vertical transistors face a tradeoff between breakdown voltage and on-state resistance, and existing solutions do not adequately address the issue of parasitic capacitance, which affects switching efficiency and noise prevention.
Innovation Solution
Incorporating p-type intermediate regions between the drift region and the field plate electrodes in a vertical power MOSFET, which alters the electric field distribution and reduces output capacitance and charge amount, thereby improving switching efficiency and controlling the Coss-Vds curve.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the impurity concentration of the drift layer is increased to decrease the on-state resistance, then the on-state resistance is reduced, but the breakdown voltage is lowered
Solution Approach 1:
The patent introduces a field plate electrode structure that creates non-uniform electric field distribution in the drift layer. The field plate electrode, positioned above the drift layer and connected to the gate, generates a localized electric field that enhances the overall breakdown voltage without requiring a change in the overall impurity concentration profile of the drift layer, thus maintaining low on-state resistance while improving breakdown characteristics
Solution Approach 2:
The patent modifies the electric field distribution parameters by introducing the field plate electrode structure. This changes the voltage distribution across the drift layer, allowing the device to achieve higher breakdown voltage at the same impurity concentration, effectively decoupling the tradeoff between breakdown voltage and on-state resistance
2Reliability
If the impurity concentration of the drift layer is decreased to improve the breakdown voltage, then the breakdown voltage is improved, but the on-state resistance is increased
Solution Approach 1:
The field plate electrode creates a localized high-field region that enhances breakdown voltage without requiring a reduction in overall drift layer impurity concentration. This localized field enhancement allows the drift layer to maintain higher impurity content for low on-state resistance while still achieving high breakdown voltage through the field plate's electric field modification
3Reliability
If conventional structures are used to improve breakdown voltage and on-state resistance, then the tradeoff relationship is partially addressed, but parasitic capacitance is not adequately decreased
Solution Approach 1:
The patent extends the gate control into the vertical dimension by placing the field plate electrode above the drift layer, creating a three-dimensional electric field distribution. This vertical extension of the gate structure allows for better control of the depletion region and reduced parasitic capacitance between the gate and drain, while simultaneously improving breakdown voltage and on-state resistance characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively decreases parasitic capacitance, output charge amount, and maintains a desired relationship between breakdown voltage and on-state resistance, enhancing the transistor's switching efficiency and noise prevention capabilities.
Implementation Method 1
When the electric field distribution in the drift layer is changed by the presence of the field plate electrode, the breakdown voltage of the vertical transistor is improved
Data Source
AI summary
A semiconductor device includes a layer having first and second surfaces and a first type first region, a second type second region in the layer between the first region and first surface, a first type third region in the layer between the second region and first surface, first and second gate electrodes, wherein the second region is between the first and second gate electrodes, a first field plate electrode between the second surface and first gate electrode, a second field plate electrode between the second surface and second gate electrode, a first film, at least a portion between the first field plate electrode and first region, a second film at least a portion between the second field plate electrode and first region, and a second type fourth region in the first region between the first and second films. A portion of the first region is between second and fourth regions.