MOSFET Gate Overlap Layout for Scaled Semiconductor Reliability
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Solution Overview
Problem
As semiconductor devices are scaled down, the operating characteristics of MOS field effect transistors are negatively affected, leading to challenges in improving performance while maintaining high integration density.
Innovation Solution
A semiconductor device design that includes an active pattern with varying lengths on different regions of a substrate, along with specific source/drain patterns and a gate electrode with an overlapping portion, is proposed. This design aims to enhance electrical characteristics and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOS field effect transistors are scaled down to achieve high integration density, then device quantity increases, but operating characteristics deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional vertical channel structures. The gate electrode wraps around the channel in a FinFET or GAA configuration, providing electrostatic control from multiple directions. This dimensional change enables continued scaling while maintaining effective gate control and carrier transport, thus improving operating characteristics at high integration densities.
Solution Approach 2:
The gate electrode is positioned to surround and enclose the channel region, with the gate wrapping around the channel like a nested structure. This multi-directional gating provides enhanced electrostatic control over the channel, allowing for better device performance and lower leakage currents at scaled dimensions while maintaining high integration density.
2Reliability
If the gate electrode overlaps the active pattern by a large length, then electrostatic control is improved, but parasitic capacitance increases
Solution Approach 1:
The patent implements non-uniform gate overlap lengths at different regions of the active pattern. The gate electrode is designed with varying overlap dimensions - larger overlap where enhanced electrostatic control is needed, and smaller overlap where parasitic capacitance would be problematic. This localized optimization balances electrostatic control improvement with parasitic capacitance reduction.
Solution Approach 2:
The gate overlap length parameter is optimized to specific dimensional ranges that balance electrostatic control and parasitic capacitance. By controlling the gate overlap length to be within certain bounds, the patent achieves sufficient gate control for scaled devices while limiting the formation of excessive parasitic capacitance that would degrade switching performance and increase power consumption.
Data Source
AI summary
A semiconductor device includes: an active pattern extending in a first direction on a substrate; a first lower source/drain pattern and a second lower source/drain pattern provided on the active pattern and spaced apart from each other in the first direction; a first upper source/drain pattern provided on the first lower source/drain pattern; a second upper source/drain pattern provided on the second lower source/drain pattern; and a gate electrode crossing the active pattern and extending in a second direction intersecting the first direction. The gate electrode includes an overlapping portion overlapping the active pattern in a third direction perpendicular to the first direction and the second direction. A length of the overlapping portion in the second direction is less than a length of the first lower source/drain pattern in the second direction.