Enhancement MOSFET Gate Structure for Stable Reference Voltage
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Solution Overview
Problem
Existing semiconductor devices with constant current circuits using depletion and enhancement type MOSFETs face challenges in maintaining stable reference voltage due to temperature-dependent threshold voltage differences between the MOSFETs, leading to variations in manufacturing and degradation over time.
Innovation Solution
The semiconductor device incorporates a reference voltage generation circuit with depletion and enhancement type MOSFETs where the n-type impurity concentration of the channel regions is equal, and the polysilicon gate of the enhancement type MOSFET is made of non-doped polysilicon, preventing p-type impurity diffusion and reducing temperature-induced changes in the reference voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If depletion and enhancement type MOSFETs are used in a constant current circuit, then reference voltage generation is enabled, but temperature-dependent threshold voltage differences cause reference voltage instability
Solution Approach 1:
The patent changes the material parameter of the enhancement type MOSFET gate from doped polysilicon to non-doped polysilicon. This parameter change eliminates p-type impurity diffusion into the channel region, thereby stabilizing the threshold voltage against temperature variations and improving reference voltage stability in the constant current circuit.
Solution Approach 2:
The patent applies different gate material qualities to different MOSFET types within the same circuit. Specifically, the enhancement type MOSFET uses non-doped polysilicon gate while the depletion type MOSFET maintains its conventional structure. This local differentiation addresses the temperature sensitivity issue specifically where it occurs (in the enhancement type MOSFET) without affecting other circuit components.
2Reliability
If doped polysilicon is used for the enhancement type MOSFET gate, then gate conductivity is improved, but p-type impurity diffusion occurs in the channel region causing threshold voltage changes
Solution Approach 1:
The patent converts the potential harm of polysilicon gate material by using non-doped polysilicon instead of doped polysilicon. This eliminates the p-type impurity diffusion problem entirely, transforming what would be a harmful effect into a beneficial stabilization of the channel region impurity concentration and threshold voltage.
Solution Approach 2:
The patent extracts the p-type dopant from the polysilicon gate material of the enhancement type MOSFET. By using non-doped polysilicon, the source of p-type impurity diffusion is removed, preventing the harmful effect from occurring in the first place while maintaining the gate's functional requirements.
3Ease of manufacture
If conventional MOSFET structures are used, then manufacturing is simplified, but manufacturing variations and degradation over time increase
Solution Approach 1:
The patent modifies the gate material parameter of the enhancement type MOSFET from doped to non-doped polysilicon. This change improves manufacturing precision and reduces variability in reference voltage generation while maintaining compatibility with conventional MOSFET manufacturing processes, thus balancing ease of manufacture with improved consistency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration stabilizes the reference voltage, reduces manufacturing variations, and minimizes degradation over time by ensuring equal n-type impurity concentrations and preventing p-type impurity diffusion in the polysilicon gate, enhancing the reliability of the semiconductor device.
Implementation Method 1
the polysilicon gate of the enhancement type MOSFET is made of non-doped polysilicon, preventing p-type impurity diffusion
Data Source
AI summary
An enhancement type MOSFET includes: a semiconductor layer having a first main surface on one side and a second main surface on another side, and having a p-type region in a surface layer region on the side of the first main surface; an n-type source region and an n-type drain region formed at an interval from each other in a surface layer region of the p-type region; a channel region formed between the n-type source region and the n-type drain region; a gate insulating film disposed on the channel region; and a polysilicon gate formed on the gate insulating film, wherein at least a main portion of the polysilicon gate is made of non-doped polysilicon.