MOSFET Gate Trench Segmentation for Active Area Reduction
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Solution Overview
Problem
In silicon chip package structures, especially for power MOSFETs, the need to extend the drain to the front side or use a common drain structure results in the sacrifice of active area, leading to increased Rdson, which is undesirable.
Innovation Solution
A novel gate design and redistribution layer approach is implemented, where the gate is formed as a trench between the source and drain, insulated by a LOCOS layer and gate oxidation, with stacked gate trench segments isolated by a LOCOS layer, allowing for reduced active area usage and efficient electrical connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the drain is extended to the front side or a common drain structure is used, then solder balls for electrical connection can be formed on the front side, but active area is sacrificed leading to increased Rdson
Solution Approach 1:
The gate structure transitions from a planar configuration to a three-dimensional trench configuration extending into the substrate. This vertical dimension allows the gate to control current flow without occupying additional horizontal active area, thereby maintaining front-side connectivity while preserving active area for low Rdson
Solution Approach 2:
The gate is divided into multiple stacked gate trench segments (first gate trench segment, second gate trench segment) isolated by LOCOS layers. This segmentation allows independent optimization of each segment's depth and positioning, enabling effective channel control while minimizing the total active area footprint
2Ease of manufacture
If dedicated active area is sacrificed to create a drain area, then drain structure can be formed, but Rdson increases
Solution Approach 1:
The gate trench is formed extending into the substrate before final drain contact formation. This preliminary gate structure establishment allows subsequent drain area creation without compromising the gate's channel control capability, ensuring low Rdson while enabling flexible drain configuration
Solution Approach 2:
Different regions of the gate structure have different depths and configurations - the gate trench segments are positioned and sized differently to optimize local electric field distribution. This local optimization allows effective channel control in the active area while permitting drain structure formation in adjacent regions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the active area required for the drain, minimizing Rdson and enabling more efficient electrical connections, thereby improving the silicon chip package structure's performance.
Implementation Method 1
the gate (G) trench being insulated from the body well layer with a LOCOS layer
Implementation Method 2
the epitaxial layer (EPI) with a gate (G) oxidation layer (GOX)
Data Source
AI summary
A silicon chip package structure, in particular a metal-oxide-semiconductor field-effect transistor (MOSFET) and method of manufacture is provided. The disclosure provides improvements to a Chip Silicon Package (CSP) structure by reducing the active area needed to be sacrificed to create a drain area.