Power Trench MOSFET Local Quality for UIS Reliability
Solution Overview
Problem
Power trench MOSFETs face reliability issues due to avalanche breakdown, which can damage the gate oxide layer and limit breakdown voltage, especially during unclamped inductive switching (UIS) conditions, where inconsistent trench depths exacerbate power loss and safety concerns.
Innovation Solution
The design optimizes the trench structure by varying the depth and width of contact holes in active and intermediate areas, redistributing electric field intensity to prevent avalanche breakdown at trench corners, ensuring it occurs in the active area instead, thus protecting the gate oxide layer and enhancing UIS performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the trench depth in the active area and the trench depth in the termination area is made inconsistent, then the device can achieve higher breakdown voltage, but the terminal area will breakdown at a low voltage level causing reliability issues
Solution Approach 1:
The patent applies local quality by creating different trench depths in different areas: the active area has deeper trenches while the termination area has shallower trenches. This localized structural differentiation allows the active area to achieve higher breakdown voltage while the termination area maintains lower electric field intensity, preventing premature breakdown and ensuring reliable operation during UIS events.
2Device complexity
If the avalanche breakdown occurs in the termination area, then the device structure is simpler, but the power loss increases and safe operation area is reduced during UIS conditions
Solution Approach 1:
The patent implements local quality through differentiated trench structures where the termination area has optimized shallower trenches that control electric field distribution. This prevents avalanche breakdown in the termination area during UIS events, redirecting it to the active area where deeper trenches can safely handle the breakdown, thereby reducing power loss and expanding the safe operation area.
3Strength
If the trench structure is optimized for high breakdown voltage, then the avalanche breakdown voltage increases, but the electric field intensity at the bottom of trenches becomes too high causing hot carrier effects
Solution Approach 1:
The patent applies local quality by varying trench depths across different functional areas. The active area features deeper trenches that concentrate the electric field in a controlled manner to achieve high breakdown voltage, while the termination area has shallower trenches that distribute the electric field more evenly, preventing excessive field intensity and hot carrier effects at trench corners.
Solution Approach 2:
The patent utilizes the vertical dimension by creating trenches of different depths rather than varying only horizontal dimensions. This vertical dimensionality allows independent optimization of electric field distribution in the active area versus the termination area, enabling high breakdown voltage while controlling hot carrier effects through three-dimensional field management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maximizes breakdown voltage and improves UIS performance by redirecting avalanche currents away from the gate oxide layer, ensuring safe operation and prolonged device reliability.
Implementation Method 1
optimize the distribution of the electric field intensity of the power semiconductor device... prevent avalanche breakdown at trench corners, ensuring it occurs in the active area instead, thus protecting the gate oxide layer and enhancing UIS performance
Data Source
AI summary
A trench type power semiconductor device with improved breakdown voltage and UIS performance and a method for preparation the device are disclosed. The trench type power semiconductor device includes a first contact hole formed in a mesa in the active area and a second contact hole formed in a mesa in an active to termination intermediate area, where the first contact hole is deeper and wider than the second contact hole. The method comprises the steps of providing a semiconductor substrate, etching an epitaxial layer, depositing a conductive material, depositing an insulation passivation layer and etching through the insulation passivation layer.