Power MOSFET Mirror Device Threshold Voltage Matching
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Solution Overview
Problem
Conventional power MOSFETs with current sensing mirror devices face inaccuracies in current ratio sensing due to differences in threshold voltages between the mirror device and the main FET, leading to potential yield loss from fault current detection, especially during the turn-off transit period.
Innovation Solution
The implementation of an optimized layout for the mirror device with link elements interconnecting pairs of body implant regions and widening these regions to match the threshold voltage of the main FET, reducing the discrepancy in threshold voltages and enhancing manufacturing yield without requiring full mask revisions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional mirror device layout is used, then device simplicity is maintained, but threshold voltage mismatch between mirror device and main FET causes current sensing inaccuracies
Solution Approach 1:
The mirror device body implant regions are segmented into multiple regions with different doping concentrations. Specifically, first body implant regions have a first doping concentration while second body implant regions have a second doping concentration that differs from the first. This segmentation allows independent optimization of threshold voltage for each region, enabling the mirror device threshold voltage to match the main FET threshold voltage while maintaining a relatively simple overall device structure.
Solution Approach 2:
Different doping concentrations are applied to different local regions of the mirror device body. The first body implant regions use a first doping concentration while the second body implant regions use a second doping concentration. This local quality variation enables precise control of the threshold voltage distribution within the mirror device, allowing it to match the main FET's threshold voltage for accurate current sensing without requiring complete structural redesign.
2Productivity
If threshold voltage mismatch is not corrected, then manufacturing process remains simple, but yield loss occurs from fault current detection
Solution Approach 1:
The body implant regions are pre-configured with specific doping concentrations during the manufacturing process to establish the correct threshold voltage relationship between the mirror device and main FET before operation. The first and second body implant regions are formed with different doping concentrations in advance, ensuring that the threshold voltage mismatch is corrected from the outset, thereby preventing yield loss from fault current detection without requiring complex post-manufacturing adjustments.
Solution Approach 2:
The doping concentration parameter is varied across different body implant regions to control the threshold voltage. By changing the doping concentration from the first value in the first body implant regions to the second value in the second body implant regions, the threshold voltage of the mirror device is adjusted to match that of the main FET. This parameter change approach enables accurate current sensing and improved manufacturing yield while maintaining manufacturing process feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces or eliminates yield loss from fault current detection by ensuring accurate current sensing, maintaining the accuracy of the current ratio during the turn-off transit period and improving manufacturing efficiency.
Implementation Method 1
first body implant regions of the first conductivity type extending into the body region adjacent to and interposed between the first source regions, wherein a doping concentration of the first body implant regions exceeds a background doping concentration of the body region
Data Source
AI summary
A MOSFET includes a substrate having a body region of a first conductivity type. A main field effect transistor (mainFET) and a mirror device are formed in the substrate. The mainFET includes first gate trenches, first source regions of a second conductivity type adjacent to the first gate trenches, and first body implant regions of the first conductivity type extending into the body region adjacent to and interposed between the first source regions. The mirror device includes second gate trenches, second source regions of the second conductivity type adjacent to the second gate trenches, second body implant regions of the first conductivity type extending into the body region adjacent to and interposed between the second source regions, and link elements of the first conductivity type interconnecting pairs of the second body implant regions.