Integrated MOSFET-Schottky Power Semiconductor Layout
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Solution Overview
Problem
Current power semiconductor devices require an additional diode for parallel circuit formation, leading to complex manufacturing processes and higher costs due to separate packages, and the parasitic diode's small area limits electrical current capacity.
Innovation Solution
A power semiconductor device design that integrates a substrate with active, buffer, and termination regions, featuring an epitaxy layer and metal layers to form a Schottky Barrier Diode in the buffer region, which is connected to the MOSFET in the active region, enhancing current capacity and reducing manufacturing complexity by forming regions in the same package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MOSFET and diode are packaged separately, then electrical protection is provided, but manufacturing process becomes complex and cost increases
Solution Approach 1:
The patent combines the MOSFET and diode into a single integrated power semiconductor device. The diode is formed within the same semiconductor substrate as the MOSFET, with the diode anode connected to the source region and diode cathode connected to the drain region. This integration eliminates the need for separate packaging of MOSFET and diode, simplifying the manufacturing process while maintaining electrical protection functionality.
2Reliability
If MOSFET and diode are packaged separately, then electrical protection is provided, but cost increases
Solution Approach 1:
The patent combines the MOSFET and diode into a single integrated power semiconductor device. The diode is formed within the same semiconductor substrate as the MOSFET, with the diode anode connected to the source region and diode cathode connected to the drain region. This integration eliminates the need for separate packaging of MOSFET and diode, simplifying the manufacturing process while maintaining electrical protection functionality.
3Volume of moving object
If parasitic diode area is small, then device structure is compact, but electrical current capacity is limited
Solution Approach 1:
The patent extends the diode structure from a two-dimensional planar configuration to a three-dimensional structure that utilizes the vertical dimension. The diode is formed with doped regions extending through the drift region, creating a larger effective diode area without significantly increasing the device footprint. This allows the diode to handle higher electrical currents while maintaining a compact overall device structure.
4Power
If diode area is increased, then electrical current capacity increases, but device volume increases
Solution Approach 1:
The patent extends the diode structure from a two-dimensional planar configuration to a three-dimensional structure that utilizes the vertical dimension. The diode is formed with doped regions extending through the drift region, creating a larger effective diode area without significantly increasing the device footprint. This allows the diode to handle higher electrical currents while maintaining a compact overall device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This integration increases the area and current capacity of the parasitic diode, simplifies the manufacturing process, reduces costs, and enhances electrical circuit protection while maintaining performance.
Implementation Method 1
Integration of a diode with the MOSFET in a single package by using a Schottky Barrier Diode (SBD) or other diode types in the buffer region
Data Source
AI summary
A power semiconductor device includes a substrate, an epitaxy layer, a source electrode, and a first metal layer. The substrate includes an active region, a buffer region, and a termination region. The buffer region surrounds the active region, and the termination region surrounds the active region. The epitaxy layer is located on the substrate. The epitaxy layer is located in the active region, the buffer region, and the termination region. The epitaxy layer has a first conductive type. The source electrode is located in the active region. The first metal layer is located in the buffer region. The first metal layer is connected to the source electrode.