MOSFET Elliptical Spiral Drain Layout for High Voltage
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Solution Overview
Problem
Ultra high voltage devices face challenges in maintaining high breakdown voltage and low on-state resistance due to current accumulation at the source and drain terminals, leading to decreased performance and increased power loss.
Innovation Solution
The design incorporates a metal oxide semiconductor field transistor with an elliptical spiral-shaped drain region and a source region that surrounds the drain, featuring a starting portion with a curvature of 0.02 to 0.0025 1/μm, and a gate dielectric layer, which helps in reducing current accumulation and enhancing breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If interdigitated fingers shape is used for source and drain regions, then layout area is decreased, but current accumulation occurs at terminals resulting in decreased breakdown voltage
Solution Approach 1:
The drain region is designed with an elliptical spiral shape instead of conventional straight or simple curved geometries. This continuous curvature design distributes the electric field more uniformly along the current path, preventing concentration at sharp corners or terminal edges, thereby maintaining high breakdown voltage while achieving compact layout area through the spiral configuration.
Solution Approach 2:
The source region completely surrounds the drain region in a nested configuration, creating a concentric or annular structure. This nesting arrangement optimizes space utilization within the layout area while providing symmetric current distribution paths that prevent terminal accumulation effects, resolving the contradiction between compactness and electrical performance.
2Area of stationary object
If interdigitated fingers shape is used for source and drain regions, then layout area is decreased, but on-state resistance increases due to current accumulation
Solution Approach 1:
The elliptical spiral geometry of the drain region creates smooth, continuous current flow paths without sharp angles or dead zones where current could accumulate. This curved path design reduces current density hotspots that cause increased on-state resistance, while the spiral structure maintains compact footprint.
Solution Approach 2:
The starting portion of the drain region is specifically designed with controlled curvature radius (0.02 to 0.0025 1/μm) to optimize current distribution at the critical entry point. This localized geometric optimization ensures uniform current injection into the channel, preventing accumulation that would increase on-state resistance while maintaining overall compact structure.
3Shape
If large curvature is present at source terminal, then current accumulates at that point, but breakdown voltage decreases
Solution Approach 1:
The invention applies continuous curvature throughout the drain region geometry, eliminating sharp corners and straight edges that cause electric field concentration. The elliptical spiral shape maintains radius of curvature within the specified range, distributing the electric field uniformly and preventing breakdown at high-curvature points while achieving compact layout.
Solution Approach 2:
The curvature radius of the drain region is precisely controlled within the range of 0.02 to 0.0025 1/μm. This parameter optimization balances two competing requirements: sufficient curvature to prevent sharp-corner field concentration (protecting breakdown voltage) while maintaining tight spacing for compact layout area.
Data Source
AI summary
A metal oxide semiconductor field transistor including a source region, a drain region, a gate and a gate dielectric layer is provided. The drain region is located in a substrate. The drain region has an elliptical spiral shape and a starting portion of the drain region is strip or water drop or has a curvature of 0.02 to 0.0025 [1/um]. The source region located in the substrate is around the drain region. The gate is located above the substrate and between the source region and the drain region. The gate dielectric layer is located between the gate and the substrate.