MOSFET Stack Package Vertical Substrate Assembly
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Solution Overview
Problem
Conventional packaging configurations for multiple semiconductor chips result in increased package size and manufacturing costs while aiming for high-speed switching and low power dissipation, as they often require more surface area on printed circuit boards.
Innovation Solution
The configuration involves assembling multiple MOSFET devices on both sides of a printed circuit board, with specific positioning and electrical connections to maximize chip density, reduce gate resistance, and enhance thermal spreading, allowing for improved electrical performance within a given size without increasing the package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a greater number of semiconductor chips are assembled in a single semiconductor package, then electrical current performance is improved and power dissipation is reduced, but package size increases and manufacturing cost increases
Solution Approach 1:
The patent transitions from conventional two-dimensional planar arrangement of semiconductor chips to a three-dimensional stacked configuration. Multiple MOSFET chips are vertically stacked and interconnected through the substrate, enabling higher chip density within the same package footprint while improving electrical performance through reduced current paths.
Solution Approach 2:
The patent implements a nested structure where multiple MOSFET chips are stacked within a single package footprint. The chips are arranged in vertical layers with interconnections passing through intermediate layers, allowing multiple functional units to be contained within the same external package dimensions.
2Reliability
If a greater number of semiconductor chips are assembled in a single semiconductor package, then electrical current performance is improved and power dissipation is reduced, but manufacturing cost increases
Solution Approach 1:
The patent employs preliminary bonding of MOSFET chips to the substrate before final package assembly. Chips are pre-positioned and electrically interconnected in a stacked configuration prior to encapsulation, simplifying the overall manufacturing process and reducing assembly complexity despite the increased number of components.
Solution Approach 2:
The patent combines multiple MOSFET chips, substrates, and encapsulation layers into a single integrated package structure. By merging these components during the bonding and encapsulation processes, the patent achieves improved electrical performance while managing manufacturing complexity through integrated fabrication steps.
3Quantity of substance
If multiple semiconductor chips are assembled in a single semiconductor package, then chip density is improved, but surface area occupation on printed circuit board increases
Solution Approach 1:
The patent utilizes vertical stacking to increase chip density in the third dimension (height) rather than expanding the horizontal footprint. Multiple chips are arranged in vertical layers connected through the substrate, achieving high chip density while maintaining a compact package footprint that occupies minimal surface area on the printed circuit board.
Data Source
AI summary
Embodiments of the invention provide methods and configuration for packaging multiple semiconductor ships in a semiconductor package. In one embodiment, an integrated circuit system includes a printed circuit board, a first MOSFET device disposed on a first surface of the printed circuit board, and a second MOSFET device disposed on a second surface of the printed circuit board, wherein the first MOSFET device overlaps an edge of the second MOSFET device in a direction extending through the printed circuit board.