Multi-chip Stacked Package Mother Chip Eliminates Interposer
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Solution Overview
Problem
Conventional multi-chip stacked packages with interposers face issues of increased package thickness, delamination, and warpage due to CTE mismatch and poor adhesion between layers, especially when dealing with chips of different dimensions.
Innovation Solution
A two-layer mother chip structure comprising a semiconductor layer and an organic layer with an embedded redistribution layer replaces the interposer, allowing direct electrical connections between chips without additional bumps, thereby reducing package thickness and addressing adhesion and warpage issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an interposer is used to assemble multi-chip stacked package with chips of different dimensions, then electrical connections between stacked chips can be achieved, but the overall package thickness is increased and reliability issues occur due to delamination and warpage
Solution Approach 1:
The patent removes the interposer component from the multi-chip stacked package structure. By directly bonding chips of different dimensions to the substrate without an interposer, the patent eliminates the source of CTE mismatch and delamination while reducing overall package thickness. The extraction of the interposer resolves both the reliability improvement and thickness reduction goals simultaneously.
2Reliability
If an interposer is used to assemble multi-chip stacked package with chips of different dimensions, then electrical connections can be achieved, but delamination occurs due to CTE mismatch and poor adhesion between layers
Solution Approach 1:
The patent eliminates the interposer layer that causes CTE mismatch and adhesion problems. By directly bonding chips to the substrate, the patent removes the interface between dissimilar materials that leads to delamination. This simplifies the package structure while improving adhesion reliability between layers.
3Area of stationary object
If multiple chips are assembled in a single package, then footprint and volume are reduced, but the overall package thickness increases due to additional die-attaching layers
Solution Approach 1:
The patent removes the interposer and its associated die-attaching layers from the package structure. By directly bonding chips to the substrate without an interposer, the patent eliminates the thickness contribution from the interposer and its bonding layers, while maintaining the footprint reduction benefit of multi-chip stacking.
Data Source
AI summary
A multi-chip stacked package and its mother chip to save an interposer are revealed. The mother chip is a two-layer structure consisting of a semiconductor layer and an organic layer where a redistribution layer is embedded into the organic layer with a plurality of first terminals and a plurality of second terminals disposed on the redistribution layer and exposed from the organic layer. The mother chip is flip-chip mounted on the substrate. The active surface of the daughter chip is in contact with the organic layer with the bonding pads of the daughter chip bonded to the first terminals. Furthermore, a plurality of electrically connecting components electrically connect the second terminals to the substrate. In the multi-chip stacked package, the interposer can be eliminated with a thinner overall package thickness as well as controlled package warpage.