MRAM Fabrication Removing Cladding to Reduce Magnetic Interference
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Solution Overview
Problem
Current MRAM fabrication processes face challenges in scalability and cost competitiveness due to inefficiencies in the integration of CMOS and magnetic device levels, particularly in the damascene process, which requires cladding materials that can interfere with the magnetic properties of MRAM cells as circuit sizes decrease.
Innovation Solution
The proposed solution involves a new fabrication process that combines single and dual damascene Cu CMP processes to simplify the integration of word lines and vias, eliminating unnecessary cladding near MTJ cells and altering the sequence of patterning to reduce interference, thereby improving scalability and cost-effectiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional dual damascene process with cladding materials is used, then word lines and vias can be formed, but cladding materials interfere with magnetic properties of MRAM cells as circuit sizes decrease
Solution Approach 1:
The patent removes the cladding layer from the dual damascene process entirely. Instead of forming cladding materials around word lines and vias, the process directly deposits copper conductors into trenches and vias, eliminating the source of magnetic interference while maintaining structural integrity through optimized conductor deposition and planarization steps.
Solution Approach 2:
The patent changes the process parameters by eliminating the cladding material deposition step and modifying the copper conductor deposition parameters. This includes adjusting etch selectivity, conductor fill conditions, and CMP planarization parameters to achieve proper conductor formation without cladding, thereby reducing magnetic field interference in high-density MRAM arrays.
2Area of moving object
If circuit sizes are reduced to increase density, then more cells can be packed, but cladding materials have greater negative impact on magnetic properties
Solution Approach 1:
By completely removing the cladding layer from the fabrication process, the patent eliminates the parasitic magnetic effects that would otherwise intensify at smaller dimensions. This allows continued scaling of cell size and density without the diminishing returns imposed by cladding-induced magnetic interference.
3Device complexity
If single damascene process is used, then fewer process steps are required, but separate patterning of word lines and vias increases process complexity
Solution Approach 1:
The patent segments the patterning process into distinct steps: first patterning the word line trenches, depositing copper, planarizing, then patterning the via trenches, depositing copper, and planarizing again. This segmented approach replaces the complex single-step dual damascene with cladding with two simpler sequential single damascene processes, improving manufacturability while maintaining low device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the efficiency, cost-effectiveness, and scalability of MRAM device fabrication by reducing the impact of cladding materials on magnetic properties and simplifying the process flow, particularly as circuit elements shrink in size.
Implementation Method 1
a first Cu damascene process is used to form interconnecting vias (16), (17)
Implementation Method 2
a Cu CMP process is then used to remove excess Cu material about the word lines (22)
Implementation Method 3
trenches are formed in the layer or layers at either a 'single' depth or at two different, or, 'dual' depths
Data Source
AI summary
Described herein are novel, cost effective and scalable methods for integrating a CMOS level with a memory cell level to form a field induced MRAM device. The memory portion of the device includes N parallel word lines, which may be clad, overlaid by M parallel bit lines orthogonal to the word lines and individual patterned memory cells formed on previously patterned electrodes at the N×M intersections of the two sets of lines. The memory portion is integrated with a CMOS level and the connection between levels is facilitated by the formation of interconnecting vias between the N×M electrodes and corresponding pads in the CMOS level and by word line connection pads in the memory device level and corresponding metal pads in the CMOS level. Of particular importance are process steps that replace single damascene formations by dual damascene formations, different process steps for the formation of clad and unclad word lines and the formation of patterned electrodes for the memory cells prior to the patterning of the cells themselves.