MRAM Column Selection Circuit Area Reduction
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Solution Overview
Problem
Current magnetic random access memory (MRAM) technologies face challenges in reducing circuit area and minimizing leak currents while maintaining robust read/write operations, particularly when compared to traditional column selection circuit configurations.
Innovation Solution
The semiconductor storage device employs a configuration with two-circuit or three-circuit column selection circuits, including first, second, third, and fourth column selection circuits, which reduce circuit area and leak currents by strategically arranging switch transistors and control signal lines, allowing for efficient selection and connection of bit and source lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional column selection circuit configurations are used, then robust read/write operations can be maintained, but circuit area and leak currents increase
Solution Approach 1:
The patent merges the functions of multiple column selection circuits into a shared circuit structure. The first and second column selection circuits share common components with the third and fourth column selection circuits, reducing the overall circuit area while maintaining the ability to perform robust read/write operations through coordinated control of the merged circuit elements
Solution Approach 2:
The column selection circuits are designed with multi-functional capabilities where the same circuit structure can serve multiple purposes. The shared circuit elements between different column selection circuits enable them to perform both reading and writing operations across different memory blocks, reducing the total circuit area required while maintaining operational robustness
2Reliability
If traditional column selection circuit configurations are used, then robust read/write operations can be maintained, but leak currents increase
Solution Approach 1:
By merging the column selection circuits into a shared structure with common components, the patent reduces the total number of transistor switches that can potentially generate leak currents. The coordinated control mechanism ensures that only necessary switches are activated during read/write operations, minimizing leakage while maintaining operational reliability
Solution Approach 2:
The patent extracts and removes redundant circuit elements from traditional column selection configurations. By identifying and eliminating unnecessary circuit components that contribute to leak currents while maintaining core read/write functionality, the design achieves lower leakage without sacrificing operational robustness
Data Source
AI summary
A semiconductor storage device includes a first memory area; a first selection circuit which selectively connects one of first lines to one of first bit lines of the first memory area, the first lines and the first bit lines extending in a first direction; a second memory area; a second selection circuit which selectively connects one of the first lines to one of second bit lines of the second memory area, the second bit lines extending in the first direction; and a third selection circuit which selectively connects one of the first lines to a global bit line and is arranged between the first selection circuit and the second selection circuit, and configured to select the first selection circuit and the second selection circuit. The first memory area, the first selection circuit, the third selection circuit, the second selection circuit, and the second memory area are aligned in this order in the first direction.