Predicting MRAM Endurance via Redundant Cell Testing
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Solution Overview
Problem
Conventional methods for testing the endurance and quality of tunnel barrier layers in MRAM cells are destructive and ineffective, limiting the ability to predict the lifespan of MRAM arrays and ensuring storage density and performance.
Innovation Solution
A processor-implemented method for testing the endurance of perpendicular magnetic tunnel junction (p-MTJ) cells in MRAM arrays by activating a subset of cells, applying specific voltages, and monitoring for failures, allowing for the physical location of faulty cells, thereby predicting the effective lifespan of the MRAM array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional destructive testing methods are used to test tunnel barrier layer endurance, then measurement precision can be achieved, but the memory cells are damaged and cannot be used for further operation
Solution Approach 1:
The patent uses redundant memory cells as test subjects instead of testing the primary functional cells. These redundant cells are spare cells that would not be used for normal data storage operations. By performing destructive or intensive endurance testing on these copies, the system can assess tunnel barrier layer quality without compromising the operational memory array.
2Productivity
If the footprint of individual MRAM cells is decreased to increase storage density, then productivity increases, but process variability and fabrication imperfections cause greater performance variations
Solution Approach 1:
The patent performs preliminary testing on redundant memory cells before the production MRAM array is deployed. By activating and monitoring a subset of redundant cells under various stress conditions, the system can detect fabrication variations and predict the lifespan of the entire array in advance, allowing for quality control measures to be taken before the product reaches the customer.
Solution Approach 2:
The system monitors the operational status of redundant memory cells during testing and uses this feedback to predict the endurance of the tunnel barrier layers in the production array. The test results provide information about fabrication quality and process variability, which can be used to adjust manufacturing parameters or screen out defective batches.
3Productivity
If a subset of redundant memory cells is activated for testing, then the testing process becomes more efficient, but the time required to locate failed cells increases
Solution Approach 1:
The patent divides the memory array into multiple columns, with each column containing both functional memory cells and redundant test cells. By organizing the testing in this segmented structure, the system can efficiently activate and monitor specific subsets of redundant cells. When a failure occurs, the columnar organization allows for systematic identification of the failed cell's location, reducing the time required to isolate and address the problem.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables efficient and non-destructive testing of MRAM cell endurance, improving quality control and predicting the lifespan of MRAM arrays, enhancing storage density and performance by identifying and addressing fabrication variations.
Implementation Method 1
Due to the spin-polarized electron tunneling effect, the electrical resistance of a cell changes due to the orientation of the magnetic fields of the two layers.
Data Source
AI summary
A processor-implemented method, according to one embodiment, includes: activating a subset of a plurality of p-MTJ cells oriented in one or more columns of a MRAM array. Activating the subset of p-MTJ cells includes: applying a first voltage to a gate terminal of the transistor in each of the p-MTJ cells in parallel, applying a second voltage to a first end of the MTJ sensor in each of the p-MTJ cells in parallel, and applying a third voltage to a drain terminal of the transistor in each of the p-MTJ cells in parallel. The processor-implemented method also includes: monitoring the activated subset of p-MTJ cells, determining whether any of the activated p-MTJ cells have failed, and in response to determining that an activated p-MTJ cell has failed, physically locating the failed p-MTJ cell. Other systems, methods, and computer program products are described in additional embodiments.