High-Density MRAM ILD Structure for Via Step Coverage
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Solution Overview
Problem
In high-density magnetoresistive random access memory (MRAM) devices, the formation of vias with negative slope profiles during the etching of dielectric film structures leads to poor step coverage and undesired Cu void defects in the Ta/TaN barrier layer and copper seed layer deposition processes.
Innovation Solution
The implementation of a high-density MRAM device with a substrate having distinct interlayer dielectric (ILD) layers in the MRAM cell array and logic areas, where the second ILD layer in the logic area has a higher nitrogen doping concentration than in the MRAM cell array, and the use of a capping layer and protective layers to cover the magnetic tunnel junction (MTJ) structures, along with a method involving nitrogen doping and etching processes to enhance step coverage and prevent Cu void defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If different dielectric film structures are etched in the MRAM cell array area and logic area, then via formation is enabled, but negative slope profiles are formed resulting in poor step coverage
Solution Approach 1:
The patent applies local quality by providing different dielectric film structures in different areas: the MRAM cell array area has a first dielectric film structure while the logic area has a second dielectric film structure. This allows each area to be optimized independently - the MRAM area can achieve proper via profiles while the logic area maintains its own requirements, thereby solving the step coverage issue caused by uniform negative slope profiles across the entire wafer.
2Ease of manufacture
If different dielectric film structures are etched in the MRAM cell array area and logic area, then via formation is enabled, but Cu void defects are formed
Solution Approach 1:
By implementing local quality with area-specific dielectric film structures, the patent prevents Cu void defects from forming in the MRAM cell array area. The optimized dielectric structure in this area ensures proper via profiles that allow complete copper filling, eliminating the void defects that would otherwise occur with negative slope profiles.
3Device complexity
If uniform dielectric thickness is used across MRAM cell array area and logic area, then manufacturing is simplified, but step coverage deteriorates
Solution Approach 1:
The patent resolves this contradiction by abandoning uniform dielectric thickness in favor of local quality optimization. The MRAM cell array area receives a specifically designed dielectric film structure that ensures proper via profiles and step coverage, while the logic area maintains its own optimized structure. This localized approach prioritizes manufacturing precision over structural uniformity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the step coverage and reduces Cu void defects, ensuring better deposition processes for the Ta/TaN barrier and copper seed layers, thereby enhancing the reliability and performance of the MRAM device.
Implementation Method 1
the second interlayer dielectric layer in the logic area has a nitrogen doping concentration that is higher than that of the second interlayer dielectric layer in the MRAM cell array area
Data Source
AI summary
The high-density MRAM device of the present invention has a second interlayer dielectric (ILD) layer covering the capping layer in the MRAM cell array area and the logic area. The thickness of the second ILD layer in the MRAM cell array area is greater than that in the logic area. The composition of the second ILD layer in the logic area is different from the composition of the second ILD layer in the MRAM cell array area.