MRAM Cell Leakage via Spacer-Assisted Particle Extraction

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Solution Overview

Problem

During the manufacturing of magnetoresistive random access memory (MRAM) devices, undesired electrical leakage between densely-packed MRAM cells occurs due to metal re-deposition during etching operations, leading to yield degradation and reliability issues.

Innovation Solution

A method involving the formation of a spacer layer over the dielectric layer to adhere to conductive particles, followed by cutting off a part of the spacer layer to physically separate the MRAM cell pillars and remove conductive particles, thereby alleviating cell-to-cell leakage, and further enhancing this by removing a portion of the dielectric layer between neighboring pillars.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If MRAM cells are densely packed to increase memory density, then productivity and storage capacity improve, but electrical leakage between cells occurs due to metal re-deposition during etching

Engineering Contradiction:
Improvememory densityVSAvoidelectrical performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent extracts and removes conductive particles that cause leakage between MRAM cells through a multi-step etching process. The process selectively removes metal re-deposition from the dielectric layer between adjacent cells, eliminating the harmful electrical connections while preserving the dense cell arrangement.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent segments the etching process into multiple sequential steps with different etching conditions. The first etching step uses a broader etching window to remove conductive particles, while subsequent steps use more selective etching to refine the separation between cells, ensuring complete isolation without damaging the MTJ structures.

Inventive Principle:
Principle #1Segmentation

2Reliability

If etching operations are performed to remove conductive particles, then cell-to-cell leakage is reduced, but manufacturing complexity increases due to multiple etching steps

Engineering Contradiction:
Improveelectrical performanceVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple etching operations into a single integrated process flow. The first etching step that removes conductive particles is performed immediately after the deposition process without requiring separate processing equipment or additional alignment steps, thereby reducing overall manufacturing complexity despite the multi-step nature of the etching sequence.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent performs the conductive particle removal etching as a preliminary step before final patterning and device formation. By eliminating potential leakage paths early in the manufacturing sequence, the process prevents defects from propagating through subsequent fabrication steps, simplifying quality control and reducing rework requirements.

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If a spacer layer is formed to adhere to conductive particles, then particle removal effectiveness improves, but manufacturing steps increase

Engineering Contradiction:
Improveparticle removal effectivenessVSAvoidnumber of manufacturing steps
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent introduces a spacer layer as an intermediary material that facilitates selective removal of conductive particles. The spacer layer adheres to the conductive particles and serves as a handle for the etching process, enabling precise extraction of the particles without directly etching the underlying dielectric or affecting adjacent MTJ structures.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies the spacer layer selectively only in regions where conductive particles are present between MRAM cells, rather than uniformly across the entire wafer. This localized application maintains manufacturing precision where needed while minimizing the impact on overall process complexity and material usage.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20220020916A1Integrated circuit and method for manufacturing the same
Publication Date: 2022.01.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20220020916A1 patent drawing
  • US20220020916A1 patent drawing
  • US20220020916A1 patent drawing

AI summary

An integrated circuit includes a substrate, a dielectric layer over the substrate, a plurality of cells, a plurality of spacers and a plurality of conductive particles. Each of the cells includes a bottom portion in the dielectric layer and an upper portion protruding from the dielectric layer. The spacers are disposed over the dielectric layer and partially cover the upper portions of the cells, respectively. The spacers are disconnected from each other, and cover a first area of the dielectric layer and expose a second area of the dielectric layer. The conductive particles are disposed between the first area of the dielectric layer and the spacers.