MRAM Block Segmentation for Parallel Current Suppression
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Solution Overview
Problem
Existing MRAM technologies face challenges in enhancing the reliability of read data and selectivity of memory cells due to the influence of parallel currents during data reading and writing, particularly in cross-point array configurations where it is difficult to maintain equal voltages across bit lines.
Innovation Solution
The proposed MRAM configuration includes a memory cell array with a common word line and bit line pairs connected to blocks in a matrix form, employing a dual-read voltage method to suppress parallel currents and improve data determination, and a write method using distinct voltages for bit lines to enhance selectivity and prevent data destruction in non-selected cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a cross-point array configuration is used in MRAM, then high integration and fast operation are achieved, but parallel currents flow through non-selected memory cells during read operations, deteriorating the reliability of data determination
Solution Approach 1:
The memory cell array is divided into multiple blocks arranged in a matrix, with each block independently controllable through common word lines and bit line pairs. This segmentation allows selective activation of specific blocks during read/write operations, enabling suppression of parallel currents in non-selected blocks while maintaining high integration density.
Solution Approach 2:
The invention applies equal voltages to both bit lines of non-selected blocks during read operations, creating an equipotential condition that prevents current flow through non-selected memory cells. This eliminates parallel currents that would otherwise deteriorate data determination reliability, while maintaining the fast read operation capability of the cross-point architecture.
2Reliability
If equal voltages are applied to bit lines during read operations, then parallel currents are suppressed, but it is difficult to maintain exactly equal voltages in practice, affecting the reliability improvement
Solution Approach 1:
The circuit design inherently provides current suppression through its structure: by applying equal voltages to both bit lines of non-selected blocks, the symmetric configuration automatically prevents current flow without requiring external control mechanisms. The system self-regulates the current flow based on the voltage application pattern, reducing the burden on precision control.
Solution Approach 2:
The invention changes the voltage parameter application strategy by simultaneously applying equal voltages to both bit lines of non-selected blocks during read operations. This parameter change transforms the voltage distribution pattern to eliminate potential differences that would drive parallel currents, achieving reliable current suppression without requiring ultra-precise voltage matching.
3Ease of operation
If conventional write methods are used in cross-point arrays, then data writing is simple, but currents flow through non-selected memory cells, causing data destruction in those cells
Solution Approach 1:
The memory array is segmented into independently controllable blocks, allowing selective activation during write operations. By activating only the block containing the target memory cell and keeping other blocks inactive through equal voltage application to their bit lines, the invention prevents write currents from flowing through non-selected cells, thereby protecting their data integrity while maintaining simple write operation procedures.
Solution Approach 2:
The common word lines and bit line pairs serve as intermediaries that enable selective control of current flow paths. During write operations, these intermediaries are configured to direct currents only through the selected block's memory cells, preventing current flow through non-selected blocks and thus protecting their data from accidental modification.
4Reliability
If more control mechanisms are added to suppress parallel currents, then read reliability improves, but device complexity increases
Solution Approach 1:
The common word lines and bit line pairs serve multiple functions: they enable block selection during read and write operations, provide voltage equalization to suppress parallel currents, and facilitate independent block control. This multi-functionality achieves reliable parallel current suppression without adding dedicated control circuits, thereby avoiding increased device complexity.
Solution Approach 2:
The invention achieves current suppression by changing the voltage parameter application pattern rather than adding control mechanisms. By applying equal voltages to both bit lines of non-selected blocks, the system utilizes the existing circuit structure to eliminate parallel currents, improving read reliability without increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly improves the reliability of read data by reducing the impact of parallel currents and enhances the selectivity of memory cells during writing, leading to more accurate data storage and reduced risk of data destruction in non-selected cells.
Implementation Method 1
A resistance value (R+ΔR) of the magnetoresistance element when the magnetization directions of the magnetization fixed layer and the magnetization free layer are 'anti-parallel' to each other is higher than a resistance value (R) when the magnetization directions are 'parallel' to each other due to the magnetoresistance effect
Implementation Method 2
A write current IW flows through the selected memory cell 30S. More specifically, the write current IW flows between the selected first bit line SBL1 and the selected second bit line SBL2 through the in-cell interconnection 34 (write interconnection) near the magnetoresistance element 33 in the selected memory cell 30S. A write magnetic field generated by the write current IW flowing through the write interconnection 34 is applied to the magnetoresistance element 33 of the selected memory cell 30S
Data Source
AI summary
An MRAM according to the present invention has: a memory cell array; a first word line and a second word line each connected to a group of memory cells arranged in a first direction; a plurality of blocks arranged in a matrix form; a common word line connected to a group of blocks arranged in the first direction; and a bit line pair connected to a group of blocks arranged in a second direction. Each block has a plurality of memory cells, and each memory cell has a first transistor and a magnetoresistance element. Each block further has a second transistor to which the plurality of memory cells are connected in parallel. A gate of the second transistor is connected to the common word line. A gate of the first transistor is connected to the first word line. One of source/drain of the first transistor is connected to the first bit line, and the other thereof is connected to one end of the magnetoresistance element and connected to the second bit line through the second transistor. The other end of the magnetoresistance element is connected to the second word line.